Hardware Design Review Plan

Comprehensive Review Checklist & Prompts for Electronics Design Engineers

Version: 1.0

Date: May 2026

Classification: Engineering Reference Document

Total Check Points: 500+

Module 1: Schematic Review (85+ Points)
1.1 General Schematic Quality
1.2 Power Architecture & Distribution
1.3 Decoupling & Bypass Capacitors
1.4 Component Selection & Specifications
1.5 Connectivity & Net Verification
1.6 Interface Circuits
1.7 Protection Circuits
1.8 Clock & Oscillator Circuits
1.9 Reset & Supervisory Circuits
1.10 Connectors & Mechanical
1.11 Documentation & Annotation
Module 2: Signal Integrity (75+ Points)
2.1 Impedance Control
2.2 Termination Strategies
2.3 Crosstalk Management
2.4 Timing & Skew Analysis
2.5 Return Path Integrity
2.6 High-Speed Serial Links
2.7 DDR Memory Interface
2.8 Analog Signal Integrity
2.9 SI Simulation & Measurement
Module 3: Power Integrity (70+ Points)
3.1 PDN Design & Target Impedance
3.2 Decoupling Strategy
3.3 Power & Ground Planes
3.4 Voltage Regulators & Converters
3.5 Power Sequencing & Management
3.6 Current Capacity & Distribution
3.7 Transient Response & Load Step
3.8 PI Simulation & Analysis
Module 4: EMI/EMC Compliance (80+ Points)
4.1 Radiated Emissions
4.2 Conducted Emissions
4.3 Susceptibility / Immunity
4.4 Grounding Strategy
4.5 Filtering & Suppression
4.6 Shielding
4.7 Cable & Connector EMC
4.8 PCB-Level EMC Design
4.9 Regulatory Standards & Testing
Module 5: PCB Layout Review (90+ Points)
5.1 Stackup Design
5.2 Component Placement
5.3 Routing Rules & Techniques
5.4 Via Strategy
5.5 Power Distribution Layout
5.6 High-Speed Layout
5.7 Silkscreen & Solder Mask
5.8 Mechanical & Assembly
5.9 Design Rule Checks
5.10 Fabrication Output
Module 6: Thermal Management (50+ Points)
6.1 Power Dissipation Analysis
6.2 Thermal Path Design
6.3 Heat Sink & Cooling
6.4 PCB Thermal Design
6.5 Component Derating & Limits
6.6 Thermal Simulation & Verification
Module 7: DFM / DFT / Reliability (65+ Points)
7.1 Design for Manufacturing
7.2 Design for Testability
7.3 Design for Assembly
7.4 Reliability & Lifetime
7.5 Supply Chain & Lifecycle
7.6 Compliance & Certification
Appendix: Detailed Review Prompts

Module 1: Schematic Review

1.1 General Schematic Quality

1.2 Power Architecture & Distribution

1.3 Decoupling & Bypass Capacitors

1.4 Component Selection & Specifications

1.5 Connectivity & Net Verification

1.6 - 1.11 (Additional Schematic Checks)

#	Check Item	Description	Risk
1	Hierarchical structure	Schematic logically organized into functional blocks with clear hierarchy	Major
2	Sheet numbering & titles	All sheets properly numbered and titled with revision control	Minor
3	Title block completeness	Title block contains project name, revision, date, author, approver	Minor
4	Net naming convention	All nets follow consistent naming convention (e.g., VCC_3V3, SPI_CLK)	Major
5	Reference designators	Components have unique, sequential reference designators per type	Major
6	No floating pins	All IC pins connected or explicitly marked NC (No Connect)	Critical
7	Power/ground symbols	Power and ground symbols consistent and correctly used	Critical
8	Off-sheet connectors	Inter-sheet connections clearly labeled and match between sheets	Major
9	ERC clean	Electrical Rules Check passes with no errors	Critical
10	Component values shown	All passive components show values; ICs show part numbers	Major
11	Wire junction dots	Wires don't cross unnecessarily; junctions clearly marked	Minor
12	Bus notation	Buses properly labeled with bit ranges	Major

#	Check Item	Description	Risk
1	Power tree defined	Complete power tree documented showing all rails and regulators	Critical
2	Input voltage range	Input supply voltage range matches system specifications	Critical
3	Regulator selection	Regulators have adequate headroom, efficiency, and thermal performance	Critical
4	Power budget analysis	Total power consumption calculated for all operating modes	Critical
5	Voltage sequencing	Power-up/down sequences comply with IC requirements	Critical
6	Enable/PGOOD signals	Enable chains and Power Good signals correctly connected	Critical
7	Inrush current limiting	Inrush current managed (soft-start, NTC, active limiting)	Major
8	Reverse polarity protection	Input power has reverse polarity protection	Critical
9	Overcurrent protection	Fuses or current limiters protect against short circuits	Critical
10	Overvoltage protection	TVS or clamping circuits protect against transients	Major
11	Feedback resistor values	Voltage dividers set correct output voltage	Critical
12	Compensation network	Loop compensation matches regulator requirements	Critical
13	Switching frequency	Switching frequency appropriate for EMI and efficiency	Major
14	Input/output cap ESR	Capacitor ESR within regulator stability requirements	Critical

#	Check Item	Description	Risk
1	Every power pin decoupled	Each VCC/VDD pin has local decoupling (typically 100nF)	Critical
2	Bulk capacitors	Bulk caps placed at power entry points	Major
3	Values per datasheet	Decoupling values match IC manufacturer recommendations	Critical
4	Multi-value decoupling	High-speed ICs use multiple cap values for frequency coverage	Major
5	Ferrite bead isolation	Sensitive sections isolated with ferrite beads on power	Major
6	Voltage rating margin	Cap voltage rating has 2x margin over operating voltage	Critical
7	DC bias derating	MLCC capacitance derating at operating voltage considered	Major
8	Temperature rating	Cap temperature rating covers operating environment	Major

#	Check Item	Description	Risk
1	Operating temperature	All components rated for product temperature range	Critical
2	Voltage/current ratings	Ratings exceed worst-case with margin	Critical
3	Power dissipation	Components rated for actual dissipation	Critical
4	Tolerance analysis	Worst-case tolerance stack-up analyzed for critical circuits	Major
5	Availability check	Components checked for availability and lifecycle status	Major
6	Second source	Critical components have second sources identified	Major
7	Package compatibility	Footprints match selected package and pin-out	Critical
8	RoHS/REACH	All components meet compliance requirements	Major
9	Derating applied	Components derated per industry guidelines	Critical
10	Crystal specs	Load cap, frequency tolerance, stability verified	Critical
11	Inductor saturation	Saturation current exceeds peak current with margin	Critical

#	Check Item	Description	Risk
1	Pin-to-pin verification	All IC connections verified against datasheet	Critical
2	Pull-up/pull-down	Open-drain outputs have appropriate pull-ups	Critical
3	I2C pull-ups	Correct values for bus speed and capacitance	Major
4	Address conflicts	No I2C/SPI address conflicts on shared buses	Critical
5	Unused inputs tied	All unused digital inputs tied to VCC/GND	Critical
6	Level translation	Translators used between different voltage domains	Critical
7	Drive strength	Output drive sufficient for load (fan-out)	Major
8	Test points	Critical signals have test points	Minor

Refer to the HTML module pages for complete tables covering: Interface Circuits, Protection Circuits, Clock & Oscillator Circuits, Reset & Supervisory, Connectors & Mechanical, and Documentation.

Module 2: Signal Integrity (SI)

2.1 Impedance Control

2.2 Termination Strategies

2.3 - 2.9 (Additional SI Checks)

#	Check Item	Description	Risk
1	Target impedance defined	Target Z specified for each signal class (50Ω SE, 100Ω diff typical)	Critical
2	Stackup verification	Field solver confirms trace widths achieve target on selected layers	Critical
3	Impedance tolerance	±10% tolerance specified and achievable	Major
4	Via discontinuity	Via transitions analyzed; back-drilling for stubs at >5 Gbps	Critical
5	Connector matching	Connector impedance matches PCB traces	Critical
6	Dielectric accuracy	Er values match actual laminate at frequency of interest	Major
7	Diff pair symmetry	Consistent spacing maintained throughout	Critical
8	Test coupons	Impedance test coupons on manufacturing panel	Major

#	Check Item	Description	Risk
1	Type selection	Correct scheme (series/parallel/AC/on-die) selected	Critical
2	Series value	R = Z0 - Rout for series termination	Major
3	Parallel placement	At receiver end, close to pin	Critical
4	Stub length	Stubs shorter than 1/10 rise time wavelength	Critical
5	ODT settings	DDR ODT configured for topology	Critical
6	AC coupling	Cap values provide adequate low-frequency cutoff	Major

Refer to HTML module page for complete tables: Crosstalk, Timing/Skew, Return Paths, SerDes, DDR, Analog SI, Simulation.

Module 3: Power Integrity (PI)

3.1 PDN Design & Target Impedance

3.2 - 3.8 (Additional PI Checks)

#	Check Item	Description	Risk
1	Target Z calculated	Z_target = (Vdd × ripple%) / I_transient	Critical
2	Frequency coverage	PDN Z below target from DC to highest transient freq	Critical
3	Flat profile	No resonant peaks exceeding target impedance	Critical
4	Anti-resonance	Anti-resonances between cap values managed	Major
5	SSN calculated	Simultaneous switching noise within budget	Critical
6	Voltage tolerance	Total variation within IC operating range	Critical

Refer to HTML module page for complete tables: Decoupling, Planes, Regulators, Sequencing, Current, Transients, Simulation.

Module 4: EMI/EMC Compliance

4.1 Radiated Emissions

4.2 - 4.9 (Additional EMC Checks)

#	Check Item	Description	Risk
1	Clock harmonics	Harmonics of all clocks identified and risk assessed	Critical
2	Bandwidth from edges	BW = 0.35/tr spectral content analyzed	Critical
3	Loop area minimized	Current loops minimized for HF signals/power	Critical
4	SSC applied	Spread spectrum on high-frequency clocks	Major
5	Cable as antenna	Cables assessed; CM chokes applied where needed	Critical
6	Enclosure apertures	Openings sized below λ/20	Critical
7	PCB edge radiation	HF traces away from board edges (>20H)	Major

Refer to HTML module page for: Conducted, Susceptibility, Grounding, Filtering, Shielding, Cables, PCB EMC, Regulatory.

Module 5: PCB Layout Review

5.1 Stackup Design

5.2 - 5.10 (Additional Layout Checks)

#	Check Item	Description	Risk
1	Layer count adequate	Sufficient layers for all signal/power/ground needs	Critical
2	Symmetrical stackup	Symmetrical about center to prevent warpage	Critical
3	Signal-ground adjacency	Every signal layer has adjacent reference plane	Critical
4	Impedance achievable	Target impedances achievable with specified geometry	Critical
5	Material selection	Laminate appropriate for frequency requirements	Critical

Refer to HTML module page for: Placement, Routing, Vias, Power Layout, High-Speed, Silkscreen, Mechanical, DRC, Fabrication.

Module 6: Thermal Management

6.1 Power Dissipation Analysis

6.2 - 6.6 (Additional Thermal Checks)

#	Check Item	Description	Risk
1	Component dissipation	Power calculated for every significant heat source	Critical
2	Operating modes	Analysis covers idle, typical, max, burst	Critical
3	Ambient temp defined	Maximum ambient specified for calculations	Critical
4	Tj = Ta + P × θJA	Junction temperature calculated and within limits	Critical
5	15°C margin	Adequate margin between calculated Tj and Tj_max	Critical

Refer to HTML module page for: Thermal Path, Heatsinks, PCB Thermal, Derating, Simulation.

Module 7: DFM / DFT / Reliability

7.1 Design for Manufacturing

7.2 - 7.6 (Additional DFM/DFT Checks)

#	Check Item	Description	Risk
1	Minimum features	All features within fabricator capability	Critical
2	Aspect ratio	Via aspect ratio within limits	Major
3	Copper balance	40-60% density per layer for warp prevention	Major
4	Registration	Layer-to-layer registration tolerance accounted for	Major
5	Surface finish	Finish compatible with all component types	Major

Refer to HTML module page for: DFT, DFA, Reliability, Supply Chain, Compliance.

Level	Definition	Action Required
Critical	Board will not function; IC damage possible; safety issue; regulatory failure	MUST FIX before fabrication release. Stop shipment.
Major	Degraded performance; reduced reliability; intermittent issues; marginal compliance	Should fix before production. May proceed with prototype at risk.
Minor	Best practice deviation; cosmetic; optimization opportunity; documentation gap	Fix when convenient. Note for next revision.

Role	Name	Date	Signature
Design Engineer
Peer Reviewer
SI/PI Engineer
EMC Engineer
Manufacturing Engineer
Project Manager