Tutorial: Module 2.2 - Termination Strategies

Checkpoint 2.2.1: Series Termination Near Source Critical

Series termination places a resistor in series with the driver output, close to the source pin. The resistor value is chosen so that the driver output impedance plus the series resistor equals the trace characteristic impedance. This absorbs the reflected wave when it returns to the source.

Operating Principle

When a driver launches a signal, the initial wavefront amplitude is determined by the voltage divider between the driver output impedance (Ro) and the trace impedance (Zo). With series termination:

Series Termination Value:

Rs = Zo - Ro

Where: Zo = trace characteristic impedance, Ro = driver output impedance

Initial wave amplitude (at source):

V_initial = Vdd * Zo / (Ro + Rs + Zo) = Vdd * Zo / (2*Zo) = Vdd/2

Voltage at receiver (after one-way propagation):

V_receiver = V_initial * (1 + rho_L)

Where rho_L = (Z_load - Zo) / (Z_load + Zo)

For high-impedance CMOS input: rho_L = 1, so V_receiver = Vdd (full swing)

Reflected wave back at source:

V_reflected = V_initial * rho_L * rho_S

rho_S = (Rs + Ro - Zo) / (Rs + Ro + Zo) = 0 (when Rs + Ro = Zo)

Therefore: no secondary reflection - signal settles in one round trip!

Practical Resistor Values

Driver Family	Typical Ro (ohm)	For 50 ohm Zo	For 40 ohm Zo (DDR)	Recommended Part
3.3V LVCMOS (strong)	10-15	33-39	22-33	Yageo RC0402FR-0733RL
3.3V LVCMOS (weak)	25-40	10-22	0-10	Yageo RC0402FR-0722RL
1.8V LVCMOS	20-30	22-33	10-22	Yageo RC0402FR-0722RL
LVTTL	15-25	22-33	15-22	Panasonic ERJ-2GEJ330X
FPGA I/O (2mA)	200-300	Not suitable	Not suitable	Use stronger drive
FPGA I/O (8mA)	25-50	0-22	DNP (0 ohm)	Yageo RC0402FR-070RL
FPGA I/O (16mA)	12-20	33	22	Yageo RC0402FR-0733RL

Placement Requirements

Place the series resistor within 500 mil (12.7 mm) of the driver pin - preferably within 200 mil.
The trace from driver to resistor should be as short as possible (this section is unterminated).
Use 0402 (1005 metric) or 0201 (0603 metric) package size to minimize parasitic inductance and pad capacitance.
Orient the resistor so signal flow is perpendicular to the resistor body (minimizes stub).
Route the controlled-impedance trace from the FAR side of the resistor to the receiver.

100 MHz SPI clock, 1.8V LVCMOS driver (Ro=25 ohm), 50 ohm trace, 4 inches long:

Rs = 50 - 25 = 25 ohm (use standard value 22 ohm)

Resistor placed 100 mil from driver ball. Trace propagation delay = 4 inches * 170 ps/inch = 680 ps.

Signal arrives at receiver at Vdd after 680 ps. No ringing. Settled before next clock edge (5 ns period).

Part: Yageo RC0402FR-0722RL (22 ohm, 1%, 0402, 0.063W)

Series resistor placed 1.5 inches from the driver, at a convenient open area on the board. The 1.5-inch unterminated stub between driver and resistor creates a resonance at 1.6 GHz. The impedance mismatch at the resistor location causes a secondary reflection that creates 200 mV undershoot at the receiver.

Driver impedance varies with voltage: CMOS drivers have different output impedance for high and low states (Roh vs Rol). Choose Rs as a compromise: Rs = Zo - (Roh + Rol)/2. Or use a value optimized for the more critical transition.

Series termination slows down the signal: The receiver sees half voltage until the reflected wave returns. For point-to-point connections this is fine, but for multi-drop buses (multiple receivers), only the LAST receiver gets full voltage immediately - intermediate receivers see a staircase waveform.

Not suitable for bidirectional buses: Series termination only works from source to load. For bidirectional signals (like DDR DQ), use parallel termination or the IC's on-die termination (ODT).

Checkpoint 2.2.2: Parallel Termination at Receiver Critical

Parallel termination places a resistor at the far end (receiver) to ground or to a termination voltage. When the resistor equals the trace impedance, the reflection coefficient becomes zero, preventing any reflected wave.

Operating Principle

Reflection coefficient at load:

rho_L = (Z_load - Zo) / (Z_load + Zo)

When Z_load = Rt = Zo: rho_L = 0 (perfect termination)

DC current consumption:

I_term = V_signal / Rt

For 3.3V signal, 50 ohm: I = 3.3V / 50 = 66 mA per signal (HIGH)

For 1.8V signal, 50 ohm: I = 1.8V / 50 = 36 mA per signal

Power dissipation:

P = V^2 / R = (3.3)^2 / 50 = 218 mW per resistor (when driven high)

For 32-bit bus: 32 * 218 mW = 7W total termination power!

When to Use Parallel Termination

Multi-drop buses where series termination creates staircase waveforms
High-frequency signals where series termination's half-voltage settling is too slow
Bus architectures requiring immediate full-swing at all receivers (e.g., backplane buses)
Signals that must maintain DC level (no capacitive AC coupling allowed)
Bidirectional buses where both ends can be drivers

Step-by-Step Design

Determine trace Zo from stackup (e.g., 50 ohm).
Select termination resistor Rt = Zo (e.g., 50 ohm).
Calculate DC power: P = Vdd^2 / Rt per signal.
If power is excessive, consider Thevenin or AC termination alternatives.
Place resistor within 200 mil of receiver pin.
Terminate to GND (for single-ended) or to Vtt (for SSTL/HSTL interfaces).
Verify resistor power rating - use 0402 (62.5 mW max) or 0603 (100 mW) appropriately.

CML (Current Mode Logic) receiver at 10 Gbps:

Interface: 10GBASE-KR, Zdiff = 100 ohm

Termination: 100 ohm differential (two 50 ohm resistors to ground, or one 100 ohm across differential pair)

Parts: 2x Panasonic ERJ-2GEJ500X (50 ohm, 0402, 0.1W)

Power: P = (0.8Vpp)^2 / (4*100) = 1.6 mW (CML has small swing, so power is manageable)

Designer uses 50 ohm parallel termination to GND for a 3.3V LVCMOS 32-bit data bus. Total termination current: 32 * 66 mA = 2.1A. Total power: 32 * 218 mW = 7W in termination resistors alone. This also overloads the driver output stage which is not designed to source 66 mA continuously.

Checkpoint 2.2.3: Thevenin Termination Values Major

Thevenin termination uses two resistors (pull-up to Vdd and pull-down to GND) to create an equivalent termination impedance at a bias voltage of Vdd/2. This reduces DC power consumption compared to simple parallel termination while providing the same AC termination quality.

Design Equations

Thevenin equivalent impedance:

Rt = R1 || R2 = (R1 * R2) / (R1 + R2)

For matched termination: Rt = Zo

Thevenin equivalent voltage:

Vth = Vdd * R2 / (R1 + R2)

For symmetric (Vth = Vdd/2): R1 = R2 = 2 * Zo

Example for 50 ohm, 3.3V:

R1 = R2 = 2 * 50 = 100 ohm

Rt = 100 || 100 = 50 ohm

Vth = 3.3 * 100/(100+100) = 1.65V

DC Power (always flowing through divider):

P_divider = Vdd^2 / (R1 + R2) = (3.3)^2 / 200 = 54.5 mW per signal

Compare to parallel to GND: 218 mW when high, 0 when low (avg ~109 mW)

Thevenin is roughly 50% less peak power but draws power regardless of signal state

SSTL and HSTL Interfaces (DDR/QDR Memory)

Standard	Vdd	Vtt	Rt	Configuration
SSTL-2 (DDR)	2.5V	1.25V	50 ohm to Vtt	Single R to Vtt
SSTL-18 (DDR2)	1.8V	0.9V	50 ohm to Vtt	Single R to Vtt
SSTL-15 (DDR3)	1.5V	0.75V	ODT (on-die)	Internal to IC
POD12 (DDR4)	1.2V	0.6V	ODT (on-die)	Pseudo Open Drain
HSTL-I	1.5V	0.75V	50 ohm to Vtt	Single R to Vtt

Step-by-Step Design Process

Determine the required termination impedance (Rt = Zo).
Choose the desired bias point (typically Vdd/2 or specific Vtt voltage).
Calculate R1 and R2: R1 = Rt * Vdd/Vth, R2 = Rt * Vdd/(Vdd - Vth).
Select standard resistor values (may need to accept small mismatch).
Calculate actual Rt and Vth with standard values - verify within spec.
Verify power rating: each resistor dissipates Vdd^2/(4*(R1+R2)) maximum.
Place both resistors as close to the receiver pin as possible.

GTL+ bus termination (1.5V logic, 50 ohm Zo):

Vtt = 1.0V (2/3 of Vdd for GTL+ threshold optimization)

R1 (to 1.5V) = 50 * 1.5/1.0 = 75 ohm (use 75 ohm standard value)

R2 (to GND) = 50 * 1.5/(1.5-1.0) = 150 ohm (use 150 ohm standard value)

Actual Rt = 75*150/(75+150) = 50 ohm (exact match)

Actual Vth = 1.5 * 150/225 = 1.0V (exact match)

Designer uses 47 ohm and 47 ohm for Thevenin termination on a 50 ohm bus. Rt = 23.5 ohm (over-terminated by 53%). This creates a negative reflection coefficient, causing undershoot that violates the receiver's minimum input voltage specification and potentially causes latch-up.

Vtt power supply requirements: When using external Vtt supplies for SSTL/HSTL, the supply must be able to both source AND sink current (the signal swings above and below Vtt). Use a dedicated LDO with sink capability or a DDR Vtt regulator like TI TPS51200.

Thevenin power is always on: Unlike series termination, the resistor divider draws DC current regardless of signal state. For a 32-bit bus: 32 * 54.5 mW = 1.74W continuous.

Checkpoint 2.2.4: AC Termination for Clocks Major

AC termination uses a series RC network to ground at the receiver end. The capacitor blocks DC (eliminating static power consumption) while the resistor provides impedance matching at signal frequencies. This is ideal for clock signals that toggle continuously.

Design Equations

AC termination component values:

R_ac = Zo (typically 50 ohm for single-ended, 100 ohm for differential)

C_ac must be large enough to appear as short circuit at signal frequency:

Xc = 1 / (2 * pi * f * C) << R_ac

Rule of thumb: Xc ≤ Zo/10 at fundamental frequency

C ≥ 1 / (2 * pi * f * Zo/10) = 10 / (2 * pi * f * Zo)

Example: 100 MHz clock, 50 ohm trace:

C ≥ 10 / (2*pi*100e6*50) = 318 pF (use 470 pF or 1 nF)

Time constant consideration:

tau = R * C should be much greater than bit period

tau = 50 * 470e-12 = 23.5 ns (vs 10 ns period = 2.35x, adequate)

If tau is too small, the cap charges up during long sequences of same polarity

Voltage on capacitor (steady state for 50% duty cycle clock):

Vc_avg = Vdd/2 (cap charges to the average signal voltage)

When to Use AC Termination

Clock signals (periodic, always toggling, 50% duty cycle)
Power-sensitive designs where DC termination current is unacceptable
Signals that transition frequently (PRN data, encoded data streams)
Not suitable for: DC-coupled signals, signals with long idle periods, asynchronous signals that may stay static

Component Selection Guide

Clock Frequency	R (ohm)	C (pF)	Capacitor Part Number
25 MHz	50	1000-2200	Murata GRM155R71H102KA01
50 MHz	50	470-1000	Murata GRM155R71H471KA01
100 MHz	50	220-470	Murata GRM155R71C471KA01
200 MHz	50	100-220	Murata GRM155R71E221KA01
400 MHz	50	47-100	Murata GRM0335C1H470JA01
800 MHz+	50	22-47	Murata GRM0335C1E220JA01

Step-by-Step Implementation

Identify all clock signals that toggle at >10 MHz and are point-to-point connections.
Set R_ac = Zo of the trace (typically 50 ohm).
Calculate minimum C: Xc at fundamental frequency should be < Zo/10.
Select next larger standard capacitor value (always round up).
Verify time constant: tau = R*C should be > 2x the clock period.
Place RC network within 200 mil of receiver pin. R connects to signal, C connects R to ground.
Simulate to verify no excessive ringing on first few edges after idle period.

133 MHz RGMII clock, 50 ohm trace, 3.3V LVCMOS:

R = 49.9 ohm (Panasonic ERJ-2GEJ49R9X, 0402)

C = 330 pF (Xc at 133 MHz = 3.6 ohm, which is Zo/14 - good)

tau = 49.9 * 330e-12 = 16.5 ns (vs 7.5 ns period = 2.2x - adequate)

Zero DC power consumption. Clean clock waveform after 2-3 initial edges.

AC termination used on an SPI chip-select signal that can be held low for milliseconds during data transfer. After asserting CS low, the capacitor charges through the 50 ohm resistor with tau = 25 ns. Within 5*tau = 125 ns, the termination has no effect. When CS is released, the stored charge creates a voltage spike that violates input thresholds.

First-edge problem: When a clock starts after an idle period, the capacitor voltage is at 0V (or last static level). The first few edges will not be properly terminated until the capacitor charges to Vdd/2. This creates 2-3 cycles of ringing at startup.

Duty cycle sensitivity: For non-50% duty cycle signals, the average capacitor voltage shifts, reducing termination effectiveness for one edge direction. For 25%/75% duty cycle, Vc_avg shifts to approximately Vdd/4 or 3*Vdd/4.

ESR matters: Capacitor ESR adds to the termination resistance. For a 50 ohm target, if C has 5 ohm ESR, use R = 45 ohm.

Checkpoint 2.2.5: Differential Termination Critical

Differential signals require termination matched to the differential impedance. The termination can be a single resistor across the pair (simplest) or a more complex network that also provides common-mode termination.

Differential Termination Topologies

Simple differential (R across pair):

Rdiff = Zdiff (e.g., 100 ohm for LVDS, 85 ohm for PCIe)

Only terminates differential mode; common-mode reflections are not addressed.

Pi-network (R + two R to ground):

Rdiff_center = Zdiff - 2*Zcm (center resistor across pair)

Rcm = Zcm (each leg to ground)

Provides both differential and common-mode termination.

T-network (two R in series + R to ground):

R_series = Zdiff/2 - Zo_single (each series element)

R_shunt = Zcm (shunt to ground at center tap)

Common-mode impedance:

Zcm = Zodd / 2 (for loosely coupled pairs, approximately Zo/2)

Typically: Zcm = 25-30 ohm for 100 ohm differential pairs

Interface-Specific Termination Requirements

Interface	Zdiff	Termination	Notes
LVDS	100 ohm	100 ohm across pair at RX	TI SN65LVDS family has internal term option
PCIe Gen3/4/5	85 ohm	Integrated in PHY	No external termination needed
USB 2.0	90 ohm	Integrated in PHY	External 45 ohm to ground on each leg
USB 3.x TX	85 ohm	Integrated in PHY	AC coupled, PHY provides term
SATA	85 ohm	Integrated in PHY	AC coupled differential
Ethernet SGMII	100 ohm	100 ohm at RX	Often internal to PHY
HDMI/DP	100 ohm	Integrated in RX	AC coupled, TMDS signaling
CML custom	100 ohm	50 ohm each leg to Vcc-2V	External termination required

Step-by-Step Verification

For each differential interface, check the RX IC datasheet for internal termination capability.
If external termination needed: place Rdiff = Zdiff across the pair, within 200 mil of RX pins.
Verify that the differential pair trace Zdiff matches the termination value.
For AC-coupled interfaces, place termination after the DC blocking capacitors (at RX side).
If common-mode rejection is critical (e.g., high-EMI environment), add common-mode termination.
Simulate differential and common-mode return loss to verify S11 < -10 dB across bandwidth.

LVDS clock pair, 100 ohm differential, 400 MHz:

100 ohm across pair at receiver (Vishay CRCW0402100RFKED, 1%, 0402)

Placed within 100 mil of LVDS receiver pin. No common-mode termination needed (LVDS receiver has good CMRR).

Trace pair: 4.2 mil width, 6.0 mil spacing on L3 stripline = 100 ohm differential.

Designer places 100 ohm termination 1 inch away from the LVDS receiver because of space constraints near the IC. The 1-inch unterminated stub at the receiver creates a resonance at approximately 2 GHz (quarter-wave). The reflection causes jitter on 800 Mbps LVDS data, exceeding the 100 ps jitter budget.

HyperLynx: In LineSim, model differential termination using the "Termination" assignment at the receiver end. Use the differential probe to measure Zdiff at the termination point. Verify that return loss < -15 dB at fundamental frequency.

Sigrity SystemSI: Set up differential S-parameter simulation. Plot Sdd11 (differential return loss) and Scc11 (common-mode return loss). Both should be < -10 dB across the signal bandwidth.

Checkpoint 2.2.6: Open-Drain Pull-Up Sizing Major

Open-drain/open-collector outputs require an external pull-up resistor to establish the high logic level. The pull-up value must be sized to balance rise time, noise margin, power consumption, and bus loading.

Design Equations

Pull-up resistor limits:

R_min = (Vcc - Vol_max) / Iol_max

Where: Vol_max = maximum output low voltage, Iol_max = maximum sink current

R_max (from rise time requirement):

t_rise = 2.2 * R_pullup * C_total

R_max = t_rise_max / (2.2 * C_total)

Where: C_total = C_pin_driver + C_pin_receivers + C_trace + C_via

Optimal range:

R_pullup should satisfy: R_min < R_pullup < R_max

Example - I2C Standard Mode (100 kHz):

Vcc = 3.3V, Vol_max = 0.4V, Iol = 3 mA

R_min = (3.3 - 0.4) / 3e-3 = 967 ohm

C_bus = 200 pF (max per I2C spec)

t_rise_max = 1000 ns (for 100 kHz mode)

R_max = 1000e-9 / (2.2 * 200e-12) = 2273 ohm

Choose: 1.5k ohm (within 967 to 2273 ohm range)

I2C Pull-Up Quick Reference

Mode	Max Freq	Max Cb	t_rise max	R_pullup (3.3V)	R_pullup (1.8V)
Standard	100 kHz	400 pF	1000 ns	1.5k - 4.7k	1k - 2.2k
Fast	400 kHz	400 pF	300 ns	1k - 2.2k	680 - 1.5k
Fast Plus	1 MHz	550 pF	120 ns	470 - 1k	330 - 680
High Speed	3.4 MHz	100 pF	40 ns	220 - 470	180 - 330

Step-by-Step Design Process

Determine the bus capacitance: sum all pin capacitances (from datasheets) + trace capacitance (est. 1-2 pF/cm) + via capacitance (0.3-0.7 pF per via).
Calculate R_min from driver sink current capability.
Calculate R_max from rise time requirement and total bus capacitance.
Choose a standard value in the middle of the range (provides margin on both ends).
Verify noise margins: Vih_min must be reached by the pull-up, Vol_max must be met with the pull-up current.
For long buses (>10 cm), consider active pull-ups (bus buffers like PCA9615) instead of passive resistors.
Calculate power dissipation: P = Vcc^2 / R_pullup (maximum, when output is low).

I2C Fast Mode, 3.3V, 3 devices on bus:

C_total = 10pF (master) + 10pF (slave1) + 10pF (slave2) + 30pF (trace 15cm) + 3pF (3 vias) = 63 pF

t_rise = 300 ns max (Fast Mode spec)

R_max = 300e-9 / (2.2 * 63e-12) = 2165 ohm

R_min = (3.3 - 0.4) / 3e-3 = 967 ohm

Selected: 1.5k ohm (Yageo RC0402FR-071K5L)

Actual rise time: 2.2 * 1500 * 63e-12 = 208 ns (within 300 ns limit)

Designer uses 10k ohm pull-ups on I2C Fast Mode bus with 150 pF total capacitance. Rise time = 2.2 * 10000 * 150e-12 = 3300 ns = 3.3 us. This is 11x slower than the 300 ns requirement. Bus fails to reach Vih before the next clock edge, causing communication errors.

Multiple pull-ups in parallel: If each slave device has its own pull-up (common mistake in modular designs), the effective pull-up is R/N. Three 4.7k pull-ups in parallel = 1.57k. This may exceed the driver's sink current capability.

Voltage level translation: When connecting 3.3V and 1.8V I2C devices, the pull-up should go to the lower voltage (1.8V) with a level translator, or use a bidirectional level translator like TXS0102.

Bus length vs. speed: For I2C Fast Mode Plus, total bus capacitance is limited to 550 pF. At 1-2 pF/cm, this limits total trace length to approximately 275 cm (9 feet). For longer runs, use I2C bus extenders.

NXP I2C Calculator: NXP provides an online I2C pull-up calculator tool that factors in all bus parameters and recommends optimal resistor values.

HyperLynx: Model the open-drain topology with pull-up in LineSim. Use IBIS models for the open-drain driver. Sweep pull-up values to find the optimum balance of rise time and noise margin.

LTspice: Build a simple RC model: voltage source with series R_pullup, load capacitance to ground, switch (NMOS) for open-drain. Simulate rise/fall times and verify against interface spec.