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Detailed Tutorials & How-To Guides

Step-by-step instructions with real-world examples for every checkpoint

How to use these tutorials: Each submodule page provides detailed guidance for every checkpoint in that section. For each check point you'll find:

Module 1: Schematic Review 11 Sections

1.1 General Schematic Quality

Hierarchy, sheet numbering, net naming, reference designators, floating pins, ERC, junction dots, bus notation.

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1.2 Power Architecture

Power tree, input voltage range, regulator headroom, power budget, sequencing, protection circuits.

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1.3 Decoupling & Bypass

Local decoupling, bulk capacitors, value strategy, ferrite beads, ESR selection, per-pin decoupling.

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1.4 Component Selection

Voltage/current derating, temperature range, availability, second-source, moisture sensitivity, tolerance.

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1.5 Connectivity

Pin-to-pin verification, pull-up/down, unused pins, multi-function configuration, address conflicts.

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1.6 Interface Circuits

Level translation, termination, series resistors, AC coupling, common-mode chokes, timing compliance.

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1.7 Protection Circuits

ESD protection, TVS selection, clamping voltage, surge rating, thermal shutdown, fault current paths.

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1.8 Clocks & Oscillators

Crystal load caps, output frequency, distribution fan-out, jitter, guard traces, startup time.

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1.9 Reset & Supervisory

Power-on reset timing, brownout detection, watchdog, reset distribution, debouncing, documentation.

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1.10 Connectors

Pin assignment, keying, current rating, mating force, signal/ground ratio, mechanical retention.

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1.11 Documentation

BOM completeness, assembly notes, variant management, revision history, design notes, test points.

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Module 2: Signal Integrity (SI) 9 Sections

2.1 Impedance Control

Target impedance, stackup design, trace width calculation, tolerances, reference planes, discontinuities.

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2.2 Termination Strategies

Series/parallel/Thevenin/AC termination, differential termination, reflection coefficient calculations.

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2.3 Crosstalk

3W spacing rule, guard traces, layer coupling, NEXT/FEXT analysis, crosstalk budget, isolation.

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2.4 Timing & Length Matching

Setup/hold margins, flight time, length tolerance, skew budget, clock-to-data timing, group delay.

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2.5 Return Path & Reference Planes

Continuous reference planes, return vias, plane splits, void avoidance, stitching capacitors.

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2.6 SerDes & High-Speed

Channel loss, return loss, eye diagrams, TX/RX equalization, via optimization, S-parameters.

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2.7 DDR Memory Interface

DQ/DQS matching, address/command routing, write leveling, ODT, VREF, fly-by topology.

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2.8 Analog & Mixed-Signal

ADC/DAC reference, guard rings, quiet ground, filter poles, noise floor, analog/digital boundary.

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2.9 SI Simulation & Validation

IBIS models, pre/post-layout simulation, eye mask compliance, TDR measurement, correlation.

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Module 3: Power Integrity (PI) 8 Sections

3.1 PDN Design & Impedance

Target impedance, frequency-domain profile, anti-resonance, VRM bandwidth, spreading inductance.

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3.2 Decoupling Strategy

Bulk/mid/high-frequency capacitors, mounting inductance, via-in-pad, frequency coverage analysis.

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3.3 Power & Ground Planes

Plane coupling, splits, stitching caps, current density, resonance, copper weight for current.

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3.4 Voltage Regulator Design

Input/output capacitors, feedback network, compensation, inductor selection, load transient response.

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3.5 Power Sequencing

IC requirements, ramp rate, monotonic rise, power-good signals, enable timing, discharge paths.

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3.6 Current Capacity

IPC-2152 trace width, via current, plane density, thermal relief, fuse coordination, connectors.

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3.7 Transient Response

Load step response, voltage droop, recovery time, overshoot, PSRR, noise spectrum.

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3.8 PI Simulation

DC IR-drop, AC impedance, voltage ripple, power-up transient, measurement plan, correlation.

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Module 4: EMI/EMC Compliance 9 Sections

4.1 Radiated Emissions

Clock harmonics, loop area, board edge radiation, heatsink radiation, cable CM current, spectral content.

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4.2 Conducted Emissions

SMPS harmonics, input filter design, CM/DM current paths, Pi-filter design, LISN compatibility.

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4.3 Susceptibility & Immunity

ESD (IEC 61000-4-2), radiated immunity, EFT burst, surge, conducted RF, magnetic field immunity.

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4.4 Grounding Strategy

Single/multi-point grounding, chassis connection, plane segmentation, star ground, cable shields.

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4.5 EMC Filtering

Pi-filters, common-mode chokes, ferrite bead selection, feed-through caps, placement, ground return.

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4.6 Shielding

Enclosure SE, aperture leakage, seam/gasket design, cable penetration, local shields, grounding.

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4.7 Cables & Connectors (EMC)

Cable shield bonding, connector shells, filtered pins, segregation, CM ferrites, cable resonance.

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4.8 PCB-Level EMC

20H rule, stitching vias, plane split avoidance, component placement, return path stitching, guard rings.

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4.9 Regulatory Compliance

FCC/CE standards, emissions class, test plan, pre-compliance, labeling, documentation package.

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Module 5: PCB Layout Review 10 Sections

5.1 Stackup Design

Layer count, signal/ground/power arrangement, symmetry, dielectric thickness, copper weight, materials.

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5.2 Component Placement

Functional grouping, signal flow, decoupling adjacency, thermal awareness, height restrictions.

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5.3 Routing Rules

Trace widths, clearances, differential routing, length matching, angle constraints, BGA escape.

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5.4 Via Strategy

Via types, via-in-pad, current rating, anti-pad clearance, stitching vias, thermal vias, back-drill.

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5.5 Power Distribution Layout

Power plane shapes, bottleneck avoidance, decoupling via placement, Kelvin sense, star points.

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5.6 High-Speed Signal Layout

Impedance-controlled traces, reference continuity, length matching, diff pair symmetry, no stubs.

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5.7 Silkscreen & Solder Mask

Ref-des visibility, polarity marks, pin 1 indicators, mask clearance, fine-pitch mask, pad overlap.

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5.8 Mechanical Fit

Board outline, mounting holes, connector positions, keep-out zones, edge clearance, tooling holes.

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5.9 DRC Verification

DRC resolution, clearance violations, unconnected nets, manufacturing DRC, copper-to-edge, drill clearance.

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5.10 Fabrication Outputs

Gerber generation, drill files, pick-and-place, IPC netlist, fab drawings, stackup spec, assembly drawings.

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Module 6: Thermal Management 6 Sections

6.1 Power Dissipation Analysis

IC power, MOSFET losses, resistor I²R, inductor losses, total power budget, worst-case scenarios.

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6.2 Thermal Path Design

Rth_ja path, thermal pad connections, thermal vias, TIM selection, copper spreading, Rth calculations.

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6.3 Heatsink & Cooling

Heatsink Rth, airflow requirements, fan selection, natural convection, mounting, thermal grease.

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6.4 PCB Thermal Design

Thermal vias, copper pour, inner layer connections, thermal relief, hot spots, board-level Rth.

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6.5 Component Derating

Temperature derating, cap lifetime, MOSFET SOA, junction margin, connector derating, resistor power.

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6.6 Thermal Simulation

CFD/FEA simulation, boundary conditions, thermal camera validation, measurement points, correlation.

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Module 7: DFM / DFT / Reliability 6 Sections

7.1 Design for Manufacturing

Trace/space minimums, annular ring, aspect ratio, copper balance, acid traps, slivers, panelization.

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7.2 Design for Test

Test points, ICT grid spacing, boundary scan, bed-of-nails, functional test, coverage estimation.

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7.3 Design for Assembly

Orientation, reflow compatibility, wave solder, tombstoning prevention, BGA rework, fiducials.

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7.4 Reliability & Lifetime

MTBF estimation, solder fatigue, conformal coating, HALT/HASS, vibration/shock, corrosion protection.

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7.5 Supply Chain

Component availability, lead times, second sources, lifecycle status, REACH/RoHS, counterfeit mitigation.

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7.6 Compliance & Documentation

Safety certification (UL/CE), environmental compliance, EMC marking, labeling, technical file, DoC.

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