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Module 4.5 - EMC Filtering

Design review checkpoints for selecting and implementing EMC filters at power inputs, signal interfaces, and enclosure boundaries

4.5.1 Pi-Filter at Power Input Critical

Every power input to the product requires an EMC filter to prevent conducted emissions from propagating to the supply and to attenuate external interference from coupling into the product. The Pi-filter topology (C-L-C) provides excellent performance for both emission and immunity because it presents low impedance at both source and load sides.

Pi-Filter Theory and Design

Pi-filter topology: C1 (input) -- L -- C2 (output)

Insertion loss:
IL = 20*log10|1 + jωL(1/R_s + 1/R_L) - ω^2*L*C1 - ω^2*L*C2 + ...|

Simplified for matched impedance (R_s = R_L = R):
IL ≈ 20*log10(1 + (f/f_c)^3) for f >> f_c
Rolloff: 60 dB/decade (3rd order)

Corner frequency:
f_c = 1/(2*pi) * (1/(L*C_total))^(1/2) where C_total = C1*C2/(C1+C2)

For symmetric Pi (C1 = C2 = C):
f_c = 1/(2*pi*sqrt(L*C/2))

Design example for 48V DC input, 500 kHz SMPS:
Required IL at 500 kHz: 60 dB
Pi-filter (60 dB/decade): need f_c where 60*log10(500/f_c) = 60
f_c = 500/10 = 50 kHz
Choose L = 100 uH, C = 1/(4*pi^2*(50e3)^2*100e-6/2) = 0.2 uF
Use C1 = C2 = 0.22 uF (standard value), L = 100 uH
Actual f_c = 1/(2*pi*sqrt(100e-6*0.11e-6)) = 48 kHz

Component Selection Criteria

Capacitor selection for Pi-filter:

Input side (C1) - facing the external world:
  - Must handle external transients (surge, EFT)
  - Voltage rating: 2x nominal input voltage minimum
  - Type: X2 film (AC mains) or C0G/X7R ceramic (DC)
  - ESR: low, but some ESR provides damping
  - Current rating: must handle ripple current

Output side (C2) - facing the internal converter:
  - Must handle SMPS switching ripple current
  - Low ESR essential for high-frequency filtering
  - Type: X7R ceramic (good to 10+ MHz) in parallel with film
  - Multiple smaller caps in parallel reduce ESL

Inductor selection:
  - Saturation current > 1.5x max DC input current
  - DCR: low enough to avoid voltage drop issues
  - Core material: ferrite (high-frequency), iron powder (high current)
  - SRF: must be above highest frequency of concern
  - Rated current includes worst-case transients (inrush)

Example component set for 48V/5A input filter:
  C1: 2x 1 uF, 100V X7R ceramic (TDK C3216X7R2A105K)
  L: 47 uH, 6A sat, (Wurth 744770147) DCR = 35 mohm
  C2: 4x 1 uF, 100V X7R + 2x 100 nF C0G (high frequency)
            

48V industrial power input with two-stage Pi-filter: Stage 1 (external): 2.2 uF ceramic X7R 100V + 100 uH inductor (6A, DCR 28 mohm) + 4.7 uF ceramic. Stage 2 (internal): 1 uF ceramic + 22 uH ferrite inductor + 2.2 uF ceramic || 100 nF C0G. Combined provides 120 dB at 500 kHz. Damping: 2.2 ohm + 10 uF across each inductor. Total DC resistance: 50 mohm (0.25W loss at 5A). System passes CISPR 32 Class B conducted with 15 dB margin.

Filter with electrolytic capacitors only: Pi-filter using 100 uF/100V electrolytic as C1 and C2. ESR = 0.5 ohm each. Above 100 kHz, capacitors are purely resistive -- no filtering! At 1 MHz, filter provides only 6 dB insertion loss (from inductor alone vs. 60 dB expected). Root cause: electrolytic SRF is 50 kHz; above that, its just a 0.5 ohm resistor. Fix: parallel ceramics (1 uF X7R) with each electrolytic.

Inrush current and saturation: At power-on, the filter capacitors appear as short circuits, causing very high inrush current through the inductor. If this exceeds the saturation current, inductance drops to near-zero, allowing even higher current. Solution: select inductor with I_sat > I_inrush, or add inrush current limiter (NTC thermistor) before the filter.

Resonance peaking: An undamped Pi-filter has a resonance peak at f_c that can amplify noise by 20-40 dB (Q-factor of 10-100). Always add damping: either a resistor in series with a large capacitor across the inductor, or use a lossy inductor core material.

4.5.2 Common-Mode Choke at Data Cables Critical

Common-mode chokes present high impedance to common-mode noise (flowing in the same direction on both conductors) while presenting minimal impedance to differential signals (flowing in opposite directions). They are essential for controlling both conducted emissions and radiated emissions from cables.

CM Choke Operating Principle

Common-mode impedance: Z_CM = j*2*pi*f * L_CM
Differential-mode impedance: Z_DM = j*2*pi*f * L_leakage ≈ 0

CM choke specifications:
- CM inductance (L_CM): 100 uH to 50 mH (frequency dependent)
- Leakage inductance: 0.5-3% of L_CM (affects DM signal)
- Rated current: must not saturate with DC + signal current
- Impedance at target frequency: key selection parameter

Impedance calculation:
For nanocrystalline core choke with L_CM = 5 mH at 100 kHz:
Z_CM at 100 kHz = 2*pi*100e3*5e-3 = 3142 ohm
Z_CM at 1 MHz = 31,420 ohm (if no core losses; actual will be lower)
Z_CM at 10 MHz = typically 500-5000 ohm (core loss limits peak impedance)

Required CM impedance for conducted emission compliance:
Z_CM_required = V_CM_noise / I_CM_allowed
If V_CM = 1V at 1 MHz and limit requires I_CM < 10 uA:
Z_CM_required = 1V / 10uA = 100 kohm (need multi-stage filtering)

CM Choke Selection for USB 2.0

Application: USB 2.0 (480 Mbps) EMC filtering

Requirements:
  - Differential signal: 480 Mbps, 400 mV amplitude
  - Must not degrade signal: insertion loss < 1 dB at 240 MHz
  - CM impedance: > 90 ohm from 100 MHz to 1 GHz
  - Rated current: 500 mA (USB current limit)
  - Package: small (0805 or 1210 preferred)

Candidate: Murata DLW21SN900HQ2 (common-mode choke, 0805 size)
  Specifications:
  - CM impedance at 100 MHz: 90 ohm
  - CM impedance at 500 MHz: 200 ohm (peak)
  - Differential insertion loss at 240 MHz: 0.5 dB
  - Rated current: 200 mA per line
  - DC resistance: 0.35 ohm per line

Alternative: TDK ACM2012-900-2P-T002
  - CM impedance at 100 MHz: 90 ohm
  - CM impedance at 1 GHz: 50 ohm
  - Rated current: 450 mA
  - Better current handling but slightly larger (0805)

Layout rules for CM choke:
  1. Place within 5 mm of connector
  2. Route D+ and D- symmetrically through the choke
  3. Ground pad connected to solid ground plane (4+ vias)
  4. Keep input and output traces separated (no coupling)
  5. Match trace lengths after choke (< 0.5 mm mismatch)
            

Ethernet port with proper CM choke: 100BASE-TX with magnetics module (built-in CM choke in transformer). Additional PCB-level CM choke (Murata DLW21HN501SQ2, 500 ohm at 100 MHz) placed between RJ45 connector and magnetics module. Provides 40 dB CM attenuation from 30-300 MHz. Cable common-mode current measured: 1.2 uA at 100 MHz (limit would allow 7 uA). System passes radiated emissions with 12 dB margin.

USB 3.0 with wrong CM choke (too much insertion loss): Designer used a CM choke intended for USB 2.0 (with 2 nH leakage inductance) on USB 3.0 SuperSpeed lines (5 Gbps). At 2.5 GHz (fundamental frequency of 5 Gbps NRZ): insertion loss = 3.8 dB per direction. USB 3.0 eye diagram fails minimum eye height requirement. Link drops to USB 2.0 speeds. Fix: use ultra-low-leakage CM choke designed for USB 3.0 (leakage < 0.3 nH), such as TDK ACM1211-302-2PL-TL01.

Impedance Measurement: Measure CM impedance using VNA or impedance analyzer. Short both windings together on one side (combine L1 and L2). Measure impedance from combined terminal to the other combined terminal. This gives 2x single-winding CM impedance. For DM measurement: connect windings in opposition (series-opposing). The measured impedance is 2x leakage inductance.

4.5.3 Ferrite Bead Selection (Impedance at Target Frequency) Major

Ferrite beads are frequency-dependent resistors that dissipate RF energy as heat rather than reflecting it. Proper selection requires matching the ferrite bead impedance curve to the interference frequency, considering DC bias effects, and ensuring the bead does not create unwanted resonances with PCB capacitance.

Ferrite Bead Impedance Model

Ferrite bead equivalent circuit:
Z(f) = R_DC + j*2*pi*f*L(f) + R_AC(f)

Where:
- R_DC = DC resistance (copper wire resistance)
- L(f) = inductance (decreases with frequency as core permeability drops)
- R_AC(f) = AC resistance (increases with frequency, represents loss)

At low frequency: Z ≈ R_DC + j*w*L (inductive)
At resonant frequency: Z = Z_peak (resistive, maximum impedance)
At high frequency: Z decreases (capacitive effects dominate)

Selection criterion:
Z(f_noise) >= required impedance
The impedance rating (e.g., "600 ohm") is typically at 100 MHz
Always check the impedance at YOUR specific noise frequency!

DC bias derating:
Most ferrite beads lose 50-90% of impedance at rated DC current!
Example: BLM18PG601 rated 600 ohm at 100 MHz, 0 mA DC bias
At 200 mA DC bias: impedance drops to ~300 ohm (50% reduction)
At rated current (500 mA): impedance may be only 100-150 ohm

Murata BLM Series Selection Guide

Murata BLM series ferrite beads - common selections:

For power supply decoupling (high current, moderate impedance):
  BLM18PG121SN1D: 120 ohm at 100 MHz, 3A rated, DCR = 30 mohm
  BLM18PG221SN1D: 220 ohm at 100 MHz, 2A rated, DCR = 50 mohm
  BLM18PG471SN1D: 470 ohm at 100 MHz, 1A rated, DCR = 100 mohm

For signal line filtering (low current, high impedance):
  BLM18PG601SN1D: 600 ohm at 100 MHz, 500 mA, DCR = 150 mohm
  BLM18AG102SN1D: 1000 ohm at 100 MHz, 300 mA, DCR = 250 mohm
  BLM18BB221SN1D: 220 ohm at 100 MHz, broadband type (high at 1 GHz)

Size options (same impedance, different current ratings):
  BLM15 series: 0402 package (0.5-2A)
  BLM18 series: 0603 package (0.5-3A)  -- most common
  BLM21 series: 0805 package (1-6A)
  BLM31 series: 1206 package (2-8A)

Selection procedure:
  1. Determine noise frequency (e.g., 48 MHz clock harmonic)
  2. Determine DC current through bead
  3. Look up impedance at noise frequency AND at rated current
  4. Ensure Z_actual > Z_required with 2x margin
  5. Check that resonance with output capacitance doesn't cause peaking
            

Ferrite Bead + Capacitor Filter Design

Common application: IC power pin decoupling

Circuit: VCC_in --[Ferrite]-- VCC_IC --[Caps]-- GND

This forms a low-pass filter:
f_c = 1 / (2*pi*sqrt(L_bead * C_decoupling))

Warning: If Q is too high, resonance peak amplifies noise!
Q = (1/R_bead) * sqrt(L_bead/C_decoupling)
For stable filter: Q < 1 (overdamped)
R_bead > sqrt(L_bead/C_decoupling)

Example: BLM18PG601 (600 ohm at 100 MHz, L ≈ 1 uH at low freq)
With 1 uF decoupling cap: f_c = 1/(2*pi*sqrt(1e-6*1e-6)) = 159 kHz
R_bead at f_c (159 kHz) ≈ 5 ohm (low -- mostly inductive)
Q = (1/5) * sqrt(1e-6/1e-6) = 0.2 (good, overdamped)

At 100 MHz: R_bead = 600 ohm (high loss = good attenuation)
Attenuation at 100 MHz ≈ 20*log10(600/(600+50)) = -0.7 dB from source
But combined with cap: forms voltage divider giving > 40 dB attenuation

FPGA VCCIO power pin with proper ferrite + cap filter: BLM18PG221SN1D (220 ohm at 100 MHz, 2A rated) in series with VCCIO supply, followed by 4x 100 nF + 1x 10 uF MLCC at the FPGA pin. At 100 MHz: ferrite provides 220 ohm series impedance; capacitors provide 0.016 ohm shunt impedance. Attenuation = 20*log10((220+50)/0.016) = 83 dB. DC current draw: 800 mA (within 2A rating with margin). DC voltage drop: 800mA * 50mohm = 40 mV (acceptable for 3.3V rail with 5% tolerance).

High-current rail with undersized ferrite bead: Processor core VCC (1.0V, 5A) filtered with BLM18PG601 (600 ohm, 500 mA rated). At 5A: ferrite core is completely saturated -- impedance drops to near zero (just DCR = 150 mohm). No EMC filtering benefit. Additionally, the 150 mohm DCR causes 750 mV drop at 5A, reducing the 1.0V rail to 0.25V! Fix: use BLM31PG121 (120 ohm at 100 MHz, 6A rated, DCR = 8 mohm) or eliminate ferrite and use proper LC filter for high-current rails.

Ferrite bead resonance with output capacitance: A ferrite bead's inductance combined with PCB parasitic capacitance (or intentional decoupling caps) creates a resonant circuit. If the ferrite's resistive component is too low at the resonant frequency, a sharp impedance peak occurs that AMPLIFIES noise at that frequency. Always simulate or check impedance curves with your actual capacitor values.

Temperature dependence: Ferrite bead impedance changes with temperature. At high temperatures (above 100C), most ferrites lose 30-50% of impedance. At very low temperatures (-40C), impedance may increase. Check datasheets for temperature curves.

4.5.4 Feed-Through Capacitors at Enclosure Boundaries Major

Feed-through capacitors (also called EMI filter capacitors or C-type filters) provide superior high-frequency filtering compared to standard capacitors because their construction eliminates the lead inductance that limits conventional capacitor performance. They are essential at enclosure penetration points where wires pass through a shielded boundary.

Feed-Through vs. Standard Capacitor Performance

Standard MLCC capacitor self-resonant frequency (SRF):
f_SRF = 1 / (2*pi*sqrt(ESL * C))
For 100 nF 0805: ESL = 0.8 nH, SRF = 1/(2*pi*sqrt(0.8e-9*100e-9)) = 564 MHz
Above SRF: capacitor becomes INDUCTIVE (no filtering)

Feed-through capacitor:
- Signal passes THROUGH the capacitor (coaxial construction)
- No lead inductance in shunt path
- Insertion loss increases monotonically with frequency
- Effective to beyond 10 GHz

Comparison at 1 GHz for 1 nF:
Standard 0603 cap: past SRF (5 GHz), still useful but ESL limits performance
Insertion loss: ~15 dB (limited by ESL)
Feed-through 1 nF: IL = 20*log10(1 + Z_line / Z_cap)
Z_cap = 1/(2*pi*1e9*1e-9) = 0.16 ohm
IL = 20*log10(1 + 50/0.16) = 50 dB (much better!)

Applications requiring feed-through capacitors:
- Power lines penetrating shielded enclosures
- DC control signals through bulkhead walls
- Any wire that must pass through a shielding boundary above 100 MHz

Selection and Installation

  1. Determine the signal characteristics: DC voltage, maximum current, signal bandwidth (filter must pass the signal while blocking noise).
  2. Select capacitance value: f_cutoff = 1/(2*pi*R_source*C). For 50 ohm source and 100 MHz cutoff: C = 32 pF. For DC power with 1 ohm source and 1 MHz cutoff: C = 160 nF.
  3. Select voltage rating: minimum 2x operating voltage (DC + peak AC).
  4. Choose package style: solder-in (for PCB), threaded bushing (for panel mount), or chip feed-through (surface mount).
  5. Install with metal body making 360-degree contact with the shielding boundary (enclosure wall, connector shell, or ground plane ring).
  6. Verify insertion loss with VNA: measure S21 of the installed feed-through in the actual enclosure.

DC power entry through shielded enclosure: 28V DC input uses Spectrum Control 51-729-315 feed-through capacitor (1 nF, 100V DC, 3A). Threaded into aluminum enclosure wall with locknut. 360-degree ground contact to enclosure. Measured insertion loss: 25 dB at 10 MHz, 45 dB at 100 MHz, 60 dB at 1 GHz. Combined with the enclosure shielding (80 dB), total system attenuation at power input exceeds 100 dB from 100 MHz to 1 GHz.

Power wire through enclosure with standard capacitor: 28V DC wire passes through grommet in enclosure wall. A 100 nF 0805 MLCC is placed on the internal PCB, 3 cm from the enclosure wall. The 3 cm wire between wall and capacitor acts as an antenna inside the enclosure, negating the shielding. At 500 MHz, the capacitor ESL (0.8 nH) limits insertion loss to 12 dB. The grommet creates a slot in the enclosure shielding. Net shielding effectiveness at power entry: only 8 dB at 500 MHz.

4.5.5 Filter Component Placement Near Connector Critical

The physical placement of filter components relative to the connector or enclosure boundary is critical. Any unfiltered conductor length between the entry point and the filter component acts as an antenna inside the product, coupling noise to internal circuits and rendering the filter ineffective at high frequencies.

Maximum Unfiltered Length Rule

Rule: Unfiltered trace length < lambda/20 at highest frequency of concern

At 1 GHz: lambda/20 = 300mm / 20 / sqrt(er_eff) = 15mm / sqrt(3.5) = 8mm
At 500 MHz: lambda/20 = 16mm
At 100 MHz: lambda/20 = 80mm

Practical rule: Place filter within 5mm of connector for frequencies to 1 GHz

Why this matters (coupling calculation):
A 20mm unfiltered trace on the PCB surface has:
- Radiation efficiency at 500 MHz: trace = lambda/30 (electrically short antenna)
- Capacitive coupling to adjacent traces: C_mutual = 0.5-2 pF per cm
- If this trace carries 10 mA of CM current at 500 MHz:
Coupled voltage to adjacent trace (1 pF, 10mm overlap):
V_coupled = I * Z_mutual = 10mA * 1/(2*pi*500e6*1e-12) = 3.18V!
This is enough to couple noise past the filter into the product.

Layout Best Practices

  1. Place filter components on the SAME side of the PCB as the connector, as close as physically possible (< 5mm from connector pins).
  2. Route the unfiltered traces (connector to filter) away from all other circuitry. Keep minimum 3x trace-height clearance from other signals.
  3. Place a ground guard ring (grounded copper pour) around the unfiltered connector-to-filter area to contain radiated coupling.
  4. Use via stitching (ground vias at lambda/20 spacing) around the filter area to prevent coupling through the substrate.
  5. Orient filter components so the "clean" (filtered) side faces toward the product interior and the "dirty" (unfiltered) side faces the connector.
  6. Maintain physical separation between filtered and unfiltered traces: never route them in parallel, especially on adjacent layers.

USB connector with filter at connector: CM choke and ESD protection placed within 3mm of USB connector pins. Filter components on same layer as connector footprint. Filtered traces (D+, D-) route inward toward USB controller on inner layer (stripline). Unfiltered trace length: 2.5mm maximum. Ground guard ring with via stitching every 2mm surrounds the connector and filter area. No coupling from unfiltered to filtered side observed up to 3 GHz in near-field scan.

Filter placed near IC instead of connector: EMI filter for Ethernet placed adjacent to the PHY chip, 4 cm from the RJ45 connector. The 4 cm unfiltered trace on the top layer couples -25 dB to the adjacent USB trace running parallel for 2 cm. At 250 MHz (Ethernet harmonic), this coupling transfers noise from Ethernet to USB interface, causing USB intermittent errors. The filter is correctly designed but incorrectly placed -- it should be at the RJ45 connector.

4.5.6 Filter Ground Return Path Short Major

Every filter component requires a low-impedance ground return path to function correctly. The filter capacitor shunts noise current to ground -- if the ground path has high inductance, the filter performance is limited by the ground impedance, not the capacitor impedance. The ground path inductance is often the limiting factor in filter performance above 100 MHz.

Ground Path Impedance Impact

Filter insertion loss with ground inductance:
IL_actual = 20*log10(Z_source / (Z_cap + Z_ground))

For ideal ground (Z_ground = 0):
100 nF at 100 MHz: Z_cap = 0.016 ohm
IL = 20*log10(50/0.016) = 70 dB (theoretical maximum)

With 1 nH ground via (single via, 1mm PCB):
Z_ground at 100 MHz = 2*pi*100e6*1e-9 = 0.63 ohm
IL = 20*log10(50/(0.016 + 0.63)) = 38 dB
LOST 32 dB due to single via inductance!

With 5 nH ground path (long trace to via, or shared via):
Z_ground at 100 MHz = 3.14 ohm
IL = 20*log10(50/3.16) = 24 dB
LOST 46 dB due to ground inductance!

Solution: Multiple vias in parallel:
4 vias (0.3mm, 1mm PCB): L_total = 1nH/4 = 0.25 nH
Z_ground at 100 MHz = 0.16 ohm
IL = 20*log10(50/0.18) = 49 dB (recovered 11 dB vs single via)

Design Rules for Filter Grounding

  1. Filter capacitor ground pad must connect to ground plane through multiple vias (minimum 2, prefer 4) placed directly at the pad.
  2. Use the largest via drill size that fits (0.3-0.5mm) to minimize via inductance.
  3. Ground plane must be on the immediately adjacent layer (not 3 layers away through prepreg and core).
  4. Do not share ground vias between filter components and other circuits. Each filter gets dedicated ground vias.
  5. For connectors with metal shells: ground the shell directly to the ground plane at the connector footprint, providing both structural ground and filter ground reference.
  6. Measure or simulate filter insertion loss in the actual PCB layout to verify ground path is not limiting performance.

CM choke with optimized ground return: Common-mode choke center-tap (Y-cap ground point) connected to ground plane via 6 x 0.4mm vias in a tight cluster directly under the component pad. Ground plane on Layer 2 (0.1mm below surface). Each via has approximately 0.5 nH inductance; 6 in parallel = 0.083 nH. At 300 MHz: Z_ground = 0.16 ohm. Filter capacitor (100 pF) Z = 5.3 ohm. Ground does not limit performance up to 1+ GHz.

Filter cap with single via 3mm from pad: 100 pF filter capacitor at connector. Ground pad connected via 3mm trace to a single 0.2mm via that connects to ground on Layer 4 (1.2mm away through 3 dielectric layers). Total ground inductance: trace (3 nH) + via (1.5 nH) = 4.5 nH. At 300 MHz: Z_ground = 8.5 ohm. Filter cap impedance at 300 MHz = 5.3 ohm. Ground impedance EXCEEDS cap impedance -- filter is completely ground-limited. Maximum achievable IL = 20*log10(50/13.8) = 11 dB instead of theoretical 19 dB.

Measuring Filter Insertion Loss In-Situ: Use a VNA with two high-impedance probes. Probe 1 connects to the trace before the filter (on the connector side). Probe 2 connects after the filter (on the IC side). Measure S21 (transmission). This gives the actual insertion loss including all parasitic effects, ground inductance, and coupling. Compare to the component datasheet insertion loss -- any difference is due to layout issues.