Tutorial 5.2: Component Placement

Introduction to Component Placement

Component placement is the single most impactful step in PCB layout. A well-placed board routes itself; a poorly-placed board cannot be saved by clever routing. Placement determines 80% of the design's signal integrity, thermal performance, and EMC compliance.

Professional placement follows a disciplined priority order and considers electrical, thermal, mechanical, and manufacturing constraints simultaneously.

Placement Priority Order

1. Mechanically fixed components: Connectors, switches, LEDs, mounting holes, board-edge constraints
2. Critical/constrained components: BGAs, processors, FPGAs, memory (placement dictates routing feasibility)
3. High-speed interface components: PHY chips, SerDes, clock generators, termination networks
4. Power supply components: Regulators, inductors, capacitors (thermal and noise considerations)
5. Decoupling capacitors: Placed immediately after their associated IC
6. General components: Resistor networks, protection devices, test points

Checkpoint: Functional Grouping Maintained

How to Verify Functional Grouping

1. Enable the ratsnest (unrouted connections) display for the entire board
2. Select all components from one schematic sheet/block - they should cluster in one board area
3. Check that the ratsnest lines between functional blocks are short and few
4. Verify inter-block connections route through defined interface zones (not scattered across the board)
5. Highlight individual nets spanning multiple blocks - they should have clear, direct paths

Functional Block Examples

Checkpoint: Signal Flow Left-to-Right / Top-to-Bottom

Signal Flow Principles

• Input connectors on left or top edge of the board
• Processing/logic in the center
• Output connectors on right or bottom edge
• Power entry on a consistent edge (left or top typical)
• Signal path flows without doubling back (no U-turns through the board)

How to Verify Signal Flow

1. Identify the main signal path from input to output (e.g., sensor > ADC > processor > DAC > output)
2. Verify this path flows in one general direction across the board
3. Check that no intermediate component forces a signal to reverse direction
4. For complex boards with multiple I/O, verify each I/O chain has a clear flow corridor
5. Examine high-speed buses: they should route in straight corridors without excessive meandering

Checkpoint: Decoupling Capacitors Adjacent to IC Pins

Decoupling Placement Rules

Optimal Decoupling Via Strategy

GOOD: Minimum loop area
  IC Power Pin
      |
      +--- short trace (<0.5mm) ---+
                                     |
                                  [Cap Pad 1]
                                  [  100nF  ]
                                  [Cap Pad 2]
                                     |
      +--- short trace (<0.5mm) ---+
      |
  IC Ground Pin (or via to ground plane)

Total loop area: < 2mm x 0.5mm = 1 sq.mm

BAD: Large loop area
  IC Power Pin
      |
      +--- long trace (5mm) --- Via --- plane trace --- Via ---+
                                                                |
                                                            [Cap Pad 1]
                                                            [  100nF  ]
                                                            [Cap Pad 2]
                                                                |
      +--- long trace (5mm) --- Via --- plane trace --- Via ---+
      |
  IC Ground Pin

Total loop area: > 10mm x 2mm = 20 sq.mm (20x WORSE!)
            

BGA Decoupling Placement Strategy

1. Under-BGA placement (preferred): 0402 capacitors placed on the bottom side directly under the BGA power/ground via pairs. Shortest possible loop inductance.
2. Perimeter placement: Capacitors placed around BGA perimeter within 2mm of the IC edge. Use when component height prevents bottom-side placement.
3. Fan-out zone: Capacitors in the BGA breakout area, connected to power/ground vias with minimal trace length.

Checkpoint: Thermal Components Away from Heat-Sensitive Parts

Thermal Zoning Rules

Temperature-Sensitive Components

• Crystal oscillators: Frequency drift of 1-5 ppm/C. Place in temperature-stable zone.
• Voltage references: Drift of 2-50 ppm/C. Keep away from thermal gradients.
• Precision ADCs: Offset drift, gain drift affected by temperature.
• Electrolytic capacitors: Life halves for every 10C above rating.
• Op-amps (precision): Input offset voltage drift of 0.1-10 uV/C.

Airflow Consideration

When forced airflow is present:

1. Place heat-sensitive components UPSTREAM (where air enters, coolest)
2. Place heat-generating components DOWNSTREAM (where air exits)
3. Never place sensitive components in the thermal wake of a hot component
4. Verify with thermal simulation that no hot spots affect critical components

Checkpoint: Height Restrictions Respected

How to Verify Height Compliance

1. Import the enclosure 3D model (STEP file) into the PCB design tool
2. Set component height rules in the constraint manager for different board regions
3. Run 3D clearance check / collision detection
4. Pay special attention to:
   • Electrolytic capacitors (tallest common component)
   • Connectors with cables attached
   • Heatsinks and thermal solutions
   • Inductors (especially shielded power inductors)
   • Transformers and common-mode chokes
5. Verify bottom-side component height if board mounts close to chassis

Common Height Constraints

Checkpoint: Analog/Digital Segregation

Segregation Implementation

1. Physical separation: Minimum 5mm gap or guard trace/ground fence between analog and digital zones
2. Ground strategy:
   • Single ground plane (preferred for most mixed-signal designs)
   • No digital return currents flow through analog ground region
   • Ground plane under analog section free of splits, slots, or via clusters
3. Power separation: Separate regulators or ferrite bead filtering for AVDD vs DVDD
4. Signal boundary: Only necessary signals cross the analog/digital boundary, at a single defined point

Checkpoint: No Components Under Heatsink/Mechanical Parts

Keep-Out Zone Requirements

Verification Steps

1. Create keep-out regions on the appropriate layer for each mechanical feature
2. Import 3D models of all mechanical parts (heatsinks, shields, connectors)
3. Run DRC to verify no components violate keep-out regions
4. Check that test points are accessible (not under shields or heatsinks)
5. Verify that rework is possible for components near mechanical features
6. Consider assembly sequence: can the heatsink/shield be installed after soldering?

Component Placement Review Workflow

Systematic Review Process

1. Mechanical compliance: All connectors, mounting holes, and mechanically-fixed components are in correct positions per the mechanical drawing
2. Functional grouping: Select each schematic page and verify corresponding components are clustered on the PCB
3. Signal flow: Trace the main signal path through the board - it should flow logically without reversal
4. Decoupling proximity: Measure distance from each decoupling cap to its associated IC pin pair
5. Thermal zoning: Identify all hot spots and verify no sensitive components are within their thermal influence zone
6. Height compliance: Run 3D interference check against enclosure model
7. Analog/digital boundary: Verify clean separation with no digital routes crossing analog zones
8. Manufacturing access: Verify adequate spacing for assembly (pick-and-place clearance, reflow profile compatibility)

Minimum Component Spacing (IPC-7351 / Assembly)

Placement Grid, Orientation & Manufacturing Optimization

Component Orientation Rules for Reflow Soldering

Placement Grid Recommendations

• Default placement grid: 0.5mm (20mil) for general components
• Fine placement grid: 0.25mm (10mil) for tight-pitch components
• Ultra-fine grid: 0.05mm (2mil) for BGA/fine-pitch alignment
• Connector placement: Use exact coordinates from mechanical drawing (off-grid is acceptable)
• Grid alignment benefit: Consistent grid aids visual inspection and simplifies manufacturing panelization

Reflow Profile Compatibility

Component placement affects reflow soldering profile requirements:

• No large mass components adjacent to small passives: The large component acts as a heat sink, delaying reflow of neighboring joints (cold joints result)
• Keep tall components away from board center: Board center reaches peak temperature first; tall components at center can shadow smaller ones on the board periphery
• Similar thermal-mass components in same zone: Components with similar mass (all 0402s together, all QFPs together) reach reflow temperature at similar times
• Shield cans after reflow: Large ground shields should be designed for post-reflow attachment (snap-on or selective solder)

Placement DFM Guidelines per Fabricator

Placement Verification Tool Commands