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Tutorial 5.1: Stackup Design

Complete guide to PCB layer stackup design, impedance control, and material selection

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Introduction to Stackup Design

The PCB stackup is the foundation of every design. It determines signal integrity performance, power distribution efficiency, EMC compliance, and manufacturability. A poorly designed stackup cannot be fixed by routing alone - it must be correct from the start.

This tutorial covers the critical checkpoints for stackup verification during a PCB layout review, with practical examples and tool-specific guidance.

Why Stackup Matters

Checkpoint: Layer Count Adequate for Complexity

Review Criteria

The layer count must meet routing density requirements with at least 20% spare via/channel capacity. It should not be over-specified (increasing cost) or under-specified (causing congestion and DRC violations).

How to Verify

  1. Count the total number of nets in the design
  2. Identify the densest component (usually a BGA) and calculate its escape routing needs
  3. Determine the number of signal layers needed: signals = (total routing length) / (available routing area per layer)
  4. Add dedicated power/ground planes for each voltage domain requiring a full plane
  5. Verify the total meets an even number (standard manufacturing requirement)

Layer Count Selection Guide

Design ComplexityTypical Layer CountIndicators
Simple (Arduino-class)2<50 components, no BGA, <200 nets, single voltage domain
Moderate (IoT, Sensors)450-200 components, QFP/QFN, 200-500 nets, 2-3 voltage domains
Complex (Embedded Linux)6200-500 components, BGA <400 pins, 500-1500 nets, DDR3
High-Complexity (SoC)8-10BGA 400-900 pins, DDR4, 1500-3000 nets, multiple high-speed interfaces
Very High (Server/FPGA)12-20+BGA 1000+ pins, DDR4/5 multi-channel, PCIe Gen4/5, >3000 nets
Good Practice

A design with a 676-pin BGA (1.0mm pitch) uses 8 layers. Signal layers have 65% utilization. Two dedicated ground planes and one power plane provide solid references. Escape routing from BGA uses only 4 signal layers with dog-bone via fan-out.

Bad Practice

Same design forced into 4 layers. Signal layers at 95% utilization. Ground plane heavily split by routing. Multiple DRC violations remain unresolved. Traces forced to route far from their reference planes. Designer adds ground stitching vias to "fix" SI issues.

Common Pitfall

Choosing layer count based on cost alone. A 4-layer board that requires 3 design revisions due to SI/EMC failures costs far more than an 6-layer board done right the first time. Budget an additional 2 layers beyond minimum routing needs for signal integrity.

Checkpoint: Signal/Ground/Power Plane Arrangement

Review Criteria

Every high-speed signal layer must have an unbroken reference plane on an immediately adjacent layer. The arrangement must provide continuous return paths and minimize layer transitions that cross reference plane boundaries.

Standard Stackup Arrangements

4-Layer Stackup (Recommended)

Layer 1 (TOP):    Signal + Components     | 1.0 oz Cu
                  --- Prepreg (4-5 mil) ---
Layer 2 (GND):    Ground Plane            | 1.0 oz Cu
                  === Core (40 mil) ===
Layer 3 (PWR):    Power Plane             | 1.0 oz Cu
                  --- Prepreg (4-5 mil) ---
Layer 4 (BOT):    Signal + Components     | 1.0 oz Cu

Total: ~62 mil (1.57 mm)
Impedance: ~50 ohm single-ended with 7 mil trace on 4 mil prepreg (Dk=4.2)

6-Layer Stackup (High-Speed Recommended)

Layer 1 (TOP):    Signal (High-Speed)     | 0.5 oz Cu
                  --- Prepreg (3.5 mil) ---
Layer 2 (GND):    Ground Plane            | 1.0 oz Cu
                  === Core (10 mil) ===
Layer 3 (SIG):    Signal (General)        | 0.5 oz Cu
                  --- Prepreg (28 mil) ---
Layer 4 (SIG):    Signal (General)        | 0.5 oz Cu
                  === Core (10 mil) ===
Layer 5 (PWR):    Power Plane             | 1.0 oz Cu
                  --- Prepreg (3.5 mil) ---
Layer 6 (BOT):    Signal (High-Speed)     | 0.5 oz Cu

Total: ~62 mil (1.57 mm)
Note: Layers 3 and 4 reference planes on adjacent layers (L2-GND, L5-PWR)

8-Layer Stackup (DDR4/PCIe)

Layer 1 (TOP):    Signal (High-Speed)     | 0.5 oz Cu
                  --- Prepreg (3 mil) ---
Layer 2 (GND):    Ground Plane            | 1.0 oz Cu
                  === Core (5 mil) ===
Layer 3 (SIG):    Signal                  | 0.5 oz Cu
                  --- Prepreg (5 mil) ---
Layer 4 (PWR):    Power Plane             | 1.0 oz Cu
                  === Core (20 mil) ===
Layer 5 (GND):    Ground Plane            | 1.0 oz Cu
                  --- Prepreg (5 mil) ---
Layer 6 (SIG):    Signal                  | 0.5 oz Cu
                  === Core (5 mil) ===
Layer 7 (PWR):    Power Plane             | 1.0 oz Cu
                  --- Prepreg (3 mil) ---
Layer 8 (BOT):    Signal (High-Speed)     | 0.5 oz Cu

Total: ~62 mil (1.57 mm)

Key Rules for Plane Arrangement

  1. Every signal layer needs an adjacent reference plane - No two signal layers should be adjacent without a plane between them for high-speed designs
  2. High-speed signals route on outer layers - Closest coupling to reference plane (thinnest dielectric)
  3. GND planes preferred over power planes as references - Ground is more continuous (no splits for multiple voltages)
  4. Power/Ground plane pairs should be tightly coupled - Provides embedded capacitance for power delivery
  5. Signals transitioning between layers must have return via - Place GND via adjacent to signal via when changing reference planes
Good: S-G-S-P-G-S-P-S (8-layer)

All signal layers have adjacent reference planes. Layer 4 (Power) and Layer 5 (Ground) are tightly coupled for embedded capacitance. High-speed signals on L1 and L8 have the thinnest dielectric to their reference planes.

Bad: S-S-G-P-P-G-S-S (8-layer)

Signal layers 1-2 and 7-8 are adjacent with no reference between them. Crosstalk between these layers will be severe. Inner signal layers have thicker dielectric to references, making impedance control difficult.

Checkpoint: Symmetrical Stackup for Warpage Prevention

Review Criteria

Stackup must be symmetric about the center axis with maximum asymmetry less than 10% of total thickness. Copper distribution, dielectric types, and thicknesses should mirror from center.

Why Symmetry Matters

During lamination, the PCB is heated to 180-200C. Different materials expand at different rates. An asymmetric stackup creates unbalanced stress that causes the board to bow or twist when cooled. IPC-6012 Class 2 allows maximum 0.75% bow/twist; Class 3 allows 0.5%.

How to Verify Symmetry

  1. Draw the stackup cross-section and identify the center line
  2. Compare each pair of layers equidistant from center:
    • Same copper weight? (e.g., L1 and L8 both 0.5 oz)
    • Same dielectric type? (e.g., both prepreg or both core)
    • Same dielectric thickness? (e.g., both 4 mil)
    • Similar copper coverage? (within 20% copper area)
  3. Check that core layers are centered or symmetrically distributed
  4. Verify copper pour/fill provides balanced coverage on mirrored layer pairs

Common Pitfall: Unbalanced Copper Fill

Even with a symmetric stackup structure, unbalanced copper fill can cause warpage. If Layer 1 has 80% copper coverage (ground fill) but Layer 8 has only 30% copper coverage (sparse routing), the board may warp. Solution: Add copper fill (hatched or solid) to balance coverage, ensuring all mirrored pairs have similar copper area within 20%.

ParameterSymmetric (Good)Asymmetric (Bad)
L1 copper weight0.5 oz1.0 oz
L8 copper weight0.5 oz0.5 oz
Top prepreg1080 + 1080 (4 mil)2116 (5 mil)
Bottom prepreg1080 + 1080 (4 mil)1080 (3 mil)
Core structureCore-Prepreg-Core (centered)All cores on top half
Warpage riskLow (<0.5%)High (>1.0%)

Checkpoint: Dielectric Thickness for Impedance Control

Review Criteria

Every controlled-impedance trace routes on the designated layer with width matching field-solver calculation within 5%. Dielectric thickness values must be from the fabricator's standard offering.

Impedance Fundamentals

Single-ended impedance (microstrip, outer layer):

Z0 = (87 / sqrt(Er + 1.41)) * ln(5.98 * H / (0.8 * W + T))

Where:
  Z0 = characteristic impedance (ohms)
  Er = dielectric constant (Dk)
  H  = dielectric height to reference plane (mils)
  W  = trace width (mils)
  T  = copper thickness (mils)

Impedance vs. Dielectric Thickness Table (FR-4, Dk=4.2)

Target Z0Dielectric (mil)Trace Width (mil)Copper (oz)Type
50 ohm SE3.55.50.5Microstrip
50 ohm SE4.06.50.5Microstrip
50 ohm SE5.08.00.5Microstrip
50 ohm SE4.05.00.5Stripline
50 ohm SE5.06.50.5Stripline
90 ohm Diff4.04.0/5.0 s0.5Microstrip
100 ohm Diff4.03.5/6.0 s0.5Microstrip
100 ohm Diff5.04.0/5.5 s0.5Stripline

Note: "s" denotes spacing between differential pair traces. All values approximate - always verify with a 2D field solver.

Manufacturer Capability Matrix

ParameterJLCPCBPCBWayAdvanced Circuits
Min dielectric3.0 mil2.5 mil3.0 mil
Impedance tolerance+/- 10%+/- 10%+/- 5% (premium)
Standard Dk (FR-4)4.2-4.5 @1GHz4.2-4.6 @1GHz4.2-4.4 @1GHz
Dk consistency+/- 0.2+/- 0.15+/- 0.1
Available prepregs1080, 2116, 76281080, 2116, 3313, 7628All standard types
Min core thickness4 mil3 mil2 mil

Step-by-Step Impedance Verification

  1. Open the stackup editor in your EDA tool
  2. Enter all dielectric thicknesses and Dk values from the fabricator specification
  3. Run the built-in impedance calculator or export to an external field solver (Si9000, Polar)
  4. For each impedance class, verify calculated width is achievable with your minimum trace/space rules
  5. Document the controlled impedance table: layer, trace width, spacing (for diff pairs), and target impedance
  6. Send stackup to fabricator for pre-production review and impedance confirmation
Altium Designer

Use Design > Layer Stack Manager. Click "Impedance" tab to define impedance profiles. Altium uses the Simberian solver for accurate results. Each impedance profile links to a net class with automatic width assignment. Export stackup as IPC-2581 for fabricator communication.

KiCad 7+

Use Board Setup > Physical Stackup. KiCad has a built-in impedance calculator under Inspect > Board Statistics or use the standalone "PCB Calculator" tool. For controlled impedance, define net classes with appropriate track widths in Board Setup > Net Classes.

Cadence Allegro

Use Setup > Cross-section to define the stackup. The integrated Allegro PCB SI tool provides field-solver impedance calculation. Define impedance constraints in the Constraint Manager under "Physical > Impedance" for automatic DRC checking.

Checkpoint: Copper Weight Per Layer Defined

Review Criteria

Copper weight per layer matches current capacity needs. Power layers should be at least 1 oz for high-current paths. Signal layers typically use 0.5-1 oz. Verification against IPC-2152 temperature rise charts is required.

Copper Weight Reference

Weight (oz)Thickness (mil)Thickness (um)Typical Use
0.5 oz0.717.5High-density signal layers, fine-pitch routing
1.0 oz1.435Standard signal/power layers, most designs
2.0 oz2.870High-current power, automotive, power supplies
3.0 oz4.2105Very high current, bus bars, power converters

Current Capacity (IPC-2152 External Layer, 10C Rise)

Trace Width0.5 oz1.0 oz2.0 oz
5 mil0.35 A0.50 A0.70 A
10 mil0.60 A0.85 A1.20 A
20 mil1.00 A1.40 A2.00 A
50 mil1.80 A2.50 A3.50 A
100 mil2.80 A4.00 A5.60 A

Note: Internal layers carry approximately 50% of the external layer capacity due to reduced convection cooling.

Common Pitfall: Mixing Copper Weights Without Adjusting Impedance

When copper weight changes between layers (e.g., 0.5 oz signal, 1.0 oz plane), the trace thickness affects impedance. A 50-ohm trace designed for 0.5 oz copper will be approximately 48 ohms if actually fabricated with 1.0 oz copper (after etching). Always specify the finished copper thickness in impedance calculations, not the base copper weight.

Checkpoint: Prepreg/Core Materials Specified

Review Criteria

Material type (FR-4, high-Tg, Rogers, Megtron) specified with Dk and Df values at operating frequency. Dk tolerance confirmed by fabricator to be within 5%.

Common Prepreg Types

StyleThickness (mil)Resin Content (%)Dk @1GHzNotes
10802.8-3.362-683.9-4.2Thin, high resin, good for thin dielectrics
21164.5-5.048-544.2-4.5Most common general-purpose prepreg
33134.0-4.555-604.0-4.3Medium weight, good flow
76287.0-7.542-484.5-4.7Thick, low resin, for spacing

Material Selection Guide

ApplicationMaterialDkDfTg (C)
General consumerStandard FR-44.2-4.50.018-0.022130-140
Automotive/IndustrialHigh-Tg FR-44.2-4.40.015-0.020170-180
High-speed (>5 Gbps)Megtron 63.6-3.80.004-0.006185
RF/MicrowaveRogers RO4350B3.480.004280
mmWave (>30 GHz)Rogers RO30033.000.001350
Mixed (RF + digital)Hybrid (Rogers + FR-4)variesvariesvaries
Good: Complete Material Specification

Fabrication note states: "Material: Isola 370HR, Dk=4.04 at 1 GHz per IPC-TM-650 2.5.5.5, Tg=180C (DSC), Td=340C. Prepreg: 2x1080 (62% RC) for controlled impedance layers. Core: 0.1mm Isola 370HR."

Bad: Vague Specification

Fabrication note states: "Material: FR-4" with no Dk value, no specific laminate brand, no Tg requirement. Fabricator uses cheapest available material with Dk anywhere from 4.0-4.8, causing impedance variation up to 15%.

Checkpoint: Controlled Impedance Layers Identified

Review Criteria

All layers carrying impedance-controlled nets are explicitly identified. Target impedance values, trace widths, and tolerances are documented in both the constraint system and fabrication drawing.

Step-by-Step Verification Process

  1. Identify all impedance-critical interfaces:
    • USB 2.0: 90 ohm differential
    • USB 3.x: 85 ohm differential
    • HDMI: 100 ohm differential
    • PCIe: 85 ohm differential
    • DDR4 (data/address): 50 ohm single-ended, 100 ohm differential (DQS)
    • Ethernet RGMII: 50 ohm single-ended
    • LVDS: 100 ohm differential
    • MIPI CSI/DSI: 100 ohm differential
  2. Map each interface to its routing layer(s)
  3. Verify constraint manager has correct impedance targets:
    • Net class or net group assignment
    • Target impedance with tolerance (typically +/- 10%)
    • Trace width and spacing values from field solver
  4. Cross-check fabrication drawing impedance table:
    • Layer number, target impedance, trace width, spacing
    • Reference plane layer identified
    • Tolerance specified (5% or 10%)
  5. Verify coupon design is included (test coupons for impedance measurement)
Altium Designer - Impedance Setup
  1. Open Layer Stack Manager > Impedance tab
  2. Click "Add Impedance Profile" for each target
  3. Select profile type: Single-Ended, Differential, or Coplanar
  4. Set target impedance and tolerance
  5. Solver calculates required width/spacing
  6. Link profile to design rules: Design Rules > Routing > Matched Net Lengths
KiCad - Impedance Control
  1. Board Setup > Physical Stackup: enter dielectric and copper values
  2. Use PCB Calculator (Tools menu) to compute trace widths
  3. Board Setup > Net Classes: create classes with computed track widths
  4. Assign nets to classes in Schematic (net class directives) or Board Setup
  5. Note: KiCad does not auto-enforce impedance - use net class width as proxy
Cadence Allegro - Impedance Constraints
  1. Setup > Cross-section: define complete stackup
  2. Setup > Constraints > Electrical > Impedance: define targets per net/bus
  3. Allegro PCB SI computes required widths automatically
  4. Enable "Impedance" DRC check in Constraint Manager
  5. Violations appear in real-time during interactive routing
Industry Standards References
  • IPC-2221B: Generic Standard on Printed Board Design - Section 6.2 covers dielectric spacing and impedance
  • IPC-2141A: Design Guide for High-Speed Controlled Impedance Circuit Boards
  • IPC-6012E: Qualification and Performance Specification - defines impedance tolerance classes
  • IPC-TM-650 2.5.5.7: Test method for characteristic impedance measurement (TDR)
  • IPC-2581C: Generic Requirements for Printed Board Assembly Products Manufacturing Description Data and Transfer Methodology (stackup communication format)

Stackup Design Review Checklist Summary

CheckpointPriorityKey Metric
Layer count adequateMajorSignal layer utilization <80%, 20% spare capacity
Plane arrangementCriticalEvery signal layer has adjacent reference plane
Stackup symmetryCriticalAsymmetry <10% of total thickness
Dielectric for impedanceCriticalCalculated Z0 within 5% of target
Copper weight definedMajorMeets IPC-2152 current/temp requirements
Materials specifiedMajorDk, Df, Tg values documented
Impedance layers identifiedCriticalAll controlled-Z nets on correct layers with correct widths

Final Verification Steps

  1. Export stackup documentation and send to fabricator for review
  2. Request impedance simulation report from fabricator
  3. Confirm all standard prepreg/core thicknesses are available
  4. Verify total board thickness meets mechanical requirements
  5. Ensure stackup is communicated clearly in fabrication drawing with cross-section diagram
Back to Module 5: PCB Layout Review | Next: 5.2 Component Placement