Stackup is symmetric about center axis; max asymmetry <10% of total thickness; verified with fabricator capability document
Critical
Impedance targets defined
Every controlled-impedance trace routes on the designated layer with width matching field-solver calculation ±5%; target values documented in constraint manager
Critical
Reference planes adjacent to signal layers
Every high-speed signal layer has an unbroken reference plane on an immediately adjacent layer; dielectric spacing ≤5 mil for standard FR-4
Critical
Layer count justified
Layer count meets routing density requirement with ≥20% spare via/channel capacity; not over-specified (cost) or under-specified (congestion forcing DRC violations)
Major
Dielectric material specified
Material type (FR-4, high-Tg, Rogers, Megtron) specified with Dk and Df values at operating frequency; Dk tolerance ≤±5% confirmed by fabricator
Major
Copper weight appropriate
Copper weight per layer matches current capacity need; power layers ≥1 oz; signal layers 0.5–1 oz; verified with IPC-2152 temperature rise charts
Major
Prepreg/core thicknesses confirmed
Prepreg and core thicknesses match fabricator standard offerings; total board thickness within specification (typically 1.6 mm ±10%); no non-standard values used
Major
Ground/power plane allocation
Dedicated, unbroken ground plane present; power plane splits do not cut return paths of high-speed signals; plane assignment documented per layer in stackup drawing
Critical
Fabricator stackup approval
Fabricator has reviewed and signed off on the stackup; confirmed they can hold impedance tolerance ±10% or tighter as specified; written confirmation on file
Critical
Mixed-signal layer separation
Analog and digital signals routed on separate layers or with ≥3× trace-width clearance; analog reference plane unbroken beneath entire analog section
Every bypass capacitor placed within 1.5 mm of its associated IC power pin; via to ground plane directly at cap pad or within 0.5 mm
Critical
Crystal placement
Crystal/oscillator placed within 5 mm of IC clock pins; no high-speed or noisy traces routed beneath crystal area; ground guard ring or copper fill present
Critical
Thermal pad accessibility
Components with thermal pads (QFN, BGA) have adequate thermal via array; via pitch ≤1.2 mm; via-in-pad filled and planarized per IPC-4761 Type VII if required
Critical
Connector edge placement
All board-edge connectors placed with mating face flush to board edge or per mechanical drawing; no interference with enclosure walls within 1 mm clearance
Major
Height restrictions respected
No component exceeds enclosure height limit; tallest components verified against mechanical keep-out zones with ≥0.5 mm clearance on both top and bottom sides
Critical
Assembly courtyard clearance
Component courtyards do not overlap; minimum 0.25 mm gap between courtyard boundaries per IPC-7351; pick-and-place nozzle clearance verified
Major
Switching regulator layout
Input cap, IC, inductor, and output cap form tight loop with area <4 cm²; current loop minimized; feedback trace routed away from switching node
Critical
Analog/digital separation
Analog components physically grouped and separated from digital by ≥5 mm or ground moat; no digital return current crosses analog ground region
Major
Test point accessibility
All test points accessible by probe on assembled board; minimum pad size 1.0 mm diameter; not obstructed by adjacent tall components within 2 mm radius
Minor
Fiducial placement
At least 3 global fiducials placed asymmetrically; local fiducials on fine-pitch components (≤0.5 mm pitch); fiducial 1.0 mm diameter with 2.0 mm solder-mask clearance
Major
Thermal management placement
Heat-generating components (regulators, power FETs) placed with thermal vias and adequate copper pour; not adjacent to temperature-sensitive components (≥10 mm separation)
Major
Component orientation consistency
All polarized passives oriented in consistent direction per board section; IC pin-1 indicators face same direction where practical; aids visual inspection and rework
Minor
Bottom-side component restrictions
Bottom-side components respect wave/selective-solder constraints; tall bottom components avoid ICT fixture interference; BGA not on bottom unless double-sided reflow process confirmed
All power traces sized per IPC-2152 for max current with ≤10 °C temperature rise; verified at minimum copper thickness after etching tolerance
Critical
Controlled impedance routing
All controlled-impedance nets routed on correct layer with calculated width; no necking or width violations exceeding ±5% of target; impedance rules annotated in design constraints
Critical
Differential pair spacing
Differential pairs maintain constant edge-to-edge spacing (≤±10% variation) throughout route; spacing matches impedance calculation; no single-ended segments >0.5 mm
Critical
No acute-angle routing
No trace bends less than 90° anywhere on the board; high-speed traces use 135° chamfers or arcs; no acid traps that could trap etchant
Major
Clearance to board edge
All copper (traces, planes, pads) maintains ≥0.25 mm clearance from board edge and routed slots; copper to V-score ≥0.4 mm; verified on all layers
Major
Return path continuity
No signal trace crosses a plane split or void without a nearby stitching via (<2 mm away); return current path verified as low-impedance for every critical net
Critical
Length matching within tolerance
All matched-length groups routed within specified skew (e.g., DDR4 DQ-to-DQS ≤±5 mil within byte lane; clock-to-address ≤±25 mil); verified in constraint report
Critical
Crosstalk spacing adequate
Parallel high-speed traces maintain ≥3× trace-width spacing (3W rule) or per simulation results; coupling length limited to <50 mm if closer spacing required
Major
No orphan copper
No floating copper islands on any layer; all copper pour connected to a net or explicitly removed; connectivity verified via DRC isolated-copper check on all layers
Major
Neck-down at BGA breakout
BGA trace neck-down length minimized (<2 mm); impedance deviation during neck-down <15% of target; documented and accepted in signal integrity analysis
Major
Teardrops applied
Teardrops added at all pad-to-trace and via-to-trace junctions; teardrop arc is smooth with no DRC spacing violations against adjacent features
Minor
Net completeness (100% routed)
Ratsnest shows 0 unrouted connections; all nets fully connected on correct layers; no open stubs present unless intentional (antenna, termination) and documented
Each power via carries ≤0.5 A (for standard 0.3 mm drill); multiple vias paralleled for higher currents; total via current capacity verified per IPC-2152
Critical
Via aspect ratio within capability
Board thickness to drill diameter ratio ≤10:1 for standard process (e.g., 1.6 mm board requires ≥0.2 mm drill); confirmed with fabricator process specification
Major
Via-in-pad treatment
Vias in SMD pads filled and planarized (IPC-4761 Type VII) to prevent solder wicking; no open vias in BGA or fine-pitch (≤0.5 mm) component pads
Critical
Stitching vias for return current
Ground stitching vias placed within 2 mm of every signal layer-transition via; at least 2 stitching vias per reference-plane change for high-speed signals
Critical
Blind/buried via usage justified
Blind/buried/microvias used only where through-hole vias cannot meet density; fabrication process (sequential lamination) confirmed feasible and costed with vendor
Major
Via annular ring adequate
Annular ring ≥0.1 mm (4 mil) for standard vias after drilling tolerance; meets IPC Class 2 minimum; outer layer annular ring ≥ inner layer annular ring
Major
Thermal relief on plane connections
Through-hole vias connected to planes via thermal reliefs (4 spokes, 0.25 mm width) for solderability; high-current connections (>1 A) use direct connect instead
Major
Via stub length minimized
For signals >5 Gbps, via stubs <10 mil or back-drilled/blind via used; stub resonance frequency verified to be above 3rd harmonic of data rate
Critical
Via spacing rules met
Via-to-pad clearance ≥0.2 mm; via-to-via drill-to-drill clearance ≥0.3 mm; no via encroaches on adjacent SMD pad solder paste area
Major
Via fence for isolation
Ground via fence surrounds RF sections and sensitive areas with spacing ≤λ/10 at highest frequency of concern; prevents cavity resonance and edge radiation
Split planes clearly defined with no high-speed signal traces crossing splits; each power island has adequate via connections (≥4 vias) to its regulator output
Critical
Star-point grounding
Analog and digital grounds connect at a single defined point near ADC/DAC; no digital return current flows through analog ground region; verified by current-path analysis
Major
Voltage drop acceptable
DC IR-drop from regulator output to furthest load <3% of nominal voltage under max current; verified by PDN simulation or manual R = ρL/A calculation
Critical
Power trace width at transitions
No power trace necks down below minimum current-rated width at any point including via fan-out, layer transitions, and pad entries; verified on all layers
Critical
Copper pour connectivity
All power copper pours connected to their net with no isolated islands; minimum connection width ≥2× signal trace minimum; verified with DRC isolated-copper check
Critical
Sense line routing (remote sense)
Voltage feedback/sense traces routed directly to load point, not tapped from power trace mid-span; sense lines are thin (≤0.15 mm), shielded from switching noise
Major
Decoupling cap return path
Decoupling capacitor ground via connects directly to nearest ground plane with no shared via; loop area between cap pads and IC power/ground pins minimized (<10 mm²)
Critical
Switching node copper minimized
Switching-node copper area kept small to minimize dV/dt radiation but sized for current capacity; no unnecessary copper expansion beyond inductor-to-FET-to-IC connection
Major
Current sharing for parallel paths
Parallel power supply outputs have equal-length, equal-width traces to common output node; current imbalance <10% between parallel paths; symmetry verified visually
Major
Ground plane integrity
No unnecessary ground plane voids under ICs; where splits exist for isolation, they are bridged at a single defined point; void boundaries do not form slot antennas (>λ/20)
DDR address/command uses fly-by topology with correct device order; data uses point-to-point; routing matches JEDEC topology requirement; write-leveling enabled for fly-by
Critical
SerDes trace length within loss budget
High-speed serial lanes (PCIe, USB3, SATA) total trace length within channel loss budget; insertion loss < specification limit at Nyquist (e.g., PCIe Gen4: <-28 dB at 8 GHz)
Critical
AC coupling cap placement
AC coupling capacitors placed symmetrically on P and N lines within 5 mm of transmitter; pads do not break differential symmetry; consistent orientation for all pairs
Major
Differential pair intra-pair skew
P-to-N length mismatch within each differential pair ≤5 mil (±0.127 mm) for multi-gigabit links; skew compensated at every layer transition and pad entry
Critical
Reference plane unbroken under high-speed
Continuous reference plane beneath all high-speed differential pairs with no splits, voids, or crossing traces within 3× the dielectric height of the signal layer
Critical
Via transition impedance control
High-speed via transitions modeled for impedance (anti-pad size, back-drill depth optimized); return loss at via <-20 dB at Nyquist frequency per channel simulation
Major
Termination resistor placement
Parallel termination resistors placed within 5 mm of receiver; series termination within 5 mm of driver; no long trace stubs (>2 mm) to termination components
Major
Clock routing isolation
Clock traces maintain ≥5× trace-width clearance from other signals; no parallel runs with data lines for >10 mm; guard traces or ground fill present on both sides
Major
Serpentine tuning quality
Length-matching serpentines use amplitude ≤3× trace width and spacing ≥3× trace width to minimize self-coupling; placed in straight segments, not at bends or pad entries
All reference designators readable and not overlapping pads or other silkscreen; minimum text height 0.8 mm, stroke width 0.15 mm; no text clipped by board edge
Minor
Polarity markings present
All polarized components (electrolytic caps, diodes, LEDs, ICs) have clear polarity indicators on silkscreen; pin-1 dot and cathode band visible after component is soldered
Major
Silkscreen not on pads
No silkscreen ink overlaps any exposed copper pad or solder paste opening; silkscreen clipped with ≥0.1 mm clearance from all pad boundaries on all layers
Major
Solder mask expansion correct
Solder mask opening expansion 0.05–0.1 mm per side (NSMD pads); mask-defined (SMD) pads use correct reduction; no mask bridging between fine-pitch pads (≤0.5 mm)
Critical
Solder mask dam between pads
Solder mask dam between adjacent pads ≥0.075 mm (3 mil) for standard process; if dam too narrow, pads grouped under single mask opening with paste-controlled separation
Critical
Connector labeling
All connectors labeled with function/interface name (e.g., "USB", "JTAG", "12V IN"); pin-1 or orientation marked; voltage/current rating on power connectors
Minor
Board identification markings
Board name, revision number, date code location, and company identification present in silkscreen or copper; UL/CE/FCC marking areas reserved if certification required
Minor
Solder paste stencil apertures
Paste apertures optimized: area ratio ≥0.66; fine-pitch pads reduced to 80–90% of pad area; QFN center pad windowed or reduced to 50–75% to prevent voiding and bridging
Major
Via tenting and coverage
Non-test vias tented with solder mask on both sides; via-in-pad vias plugged and capped; no exposed vias within solder paste stencil aperture areas that could wick solder
Board outline dimensions match mechanical drawing within ±0.1 mm; mounting holes align with enclosure standoffs; connector cutout positions verified with 3D model overlay
Critical
Mounting hole clearances
Copper keep-out around mounting holes ≥0.5 mm beyond screw head/washer outer diameter; no traces within keep-out; grounded annular ring present if chassis ground required
Major
Panel design for manufacturing
Panelization includes tooling rails ≥5 mm width, breakaway tabs with mouse-bites or V-score, fiducials on rails, and panel size within SMT machine travel limits
Major
Strain relief at flex points
No traces or vias within 1 mm of board flex/breakaway points; connector joints reinforced with mechanical tabs or epoxy; no rigid components (BGA, ceramic) spanning flex zone
Major
Heatsink mounting provisions
Heatsink mounting pads, keep-out areas, and thermal interface clearances defined; no tall components in heatsink zone; through-holes or standoffs for clip/screw mounting present
Major
Pick-and-place compatibility
All SMD components have adequate nozzle clearance (≥0.5 mm from adjacent tall parts); rotation angles limited to 0/90/180/270°; no tombstone-prone 0201s near large thermal pads
Major
Conformal coat considerations
Keep-out areas defined for connectors, switches, test points, and adjustable components that must remain uncoated; no-coat boundaries marked on silkscreen and in fab documentation
Minor
Depaneling clearance
Components placed ≥1.0 mm from V-score lines and ≥2.0 mm from routed tab edges; no stress-sensitive components (BGA, large ceramic caps) near break/score lines
DRC report shows 0 errors; all warnings individually reviewed and documented as acceptable with engineering justification for each waived item signed off by reviewer
Critical
Minimum clearance met
No trace-to-trace, trace-to-pad, or pad-to-pad clearance less than fabricator minimum (typically ≥0.1 mm / 4 mil standard; ≥0.075 mm / 3 mil advanced); zero violations
Critical
Minimum trace width met
No trace narrower than fabricator process minimum (typically 0.1 mm outer / 0.075 mm inner layers); power traces meet calculated minimum for current rating
Critical
Netlist vs schematic match
Layout netlist matches schematic netlist 100% after back-annotation; no extra or missing nets; component count and pin assignments match BOM and schematic exactly
Critical
Unconnected pins resolved
Zero unconnected pins in connectivity report; all intentional no-connects explicitly marked with NC flag; no ratsnest lines remaining anywhere on the board
Critical
Drill-to-copper clearance
All drill holes maintain ≥0.2 mm clearance to non-connected copper on all layers; anti-pad sizes verified on inner layers; no shorts from drill wander to nearby copper
Major
High-voltage clearance rules
Creepage and clearance distances meet IPC-2221 or applicable safety standard for operating voltage (e.g., ≥0.6 mm/V for >50 V peak); verified between all high-voltage nets and ground
Critical
Manufacturing rules match fabricator
DRC constraint set matches selected fabricator capability exactly (min drill, min space, min trace, min annular ring); rules not set looser than fabricator guaranteed minimums
Gerber set includes all copper layers, solder mask (top/bottom), silkscreen (top/bottom), paste (top/bottom), board outline, and drill files; file count matches expected layer count
Critical
Gerber visual verification
All Gerber layers visually inspected in independent viewer (not source EDA tool); layers align correctly; no missing features, inverted layers, or mirrored copper
Critical
Drill file accuracy
Excellon drill file contains all hole sizes; total hole count matches design; plated and non-plated holes in separate files; drill map overlaid on Gerber confirms position accuracy
Critical
Pick-and-place file generated
Centroid file includes all SMD components with X/Y/rotation/side/ref-des; coordinates spot-checked against Gerber for ≥5 components on each side to confirm accuracy
Major
Assembly drawing complete
Assembly drawing shows component outlines, reference designators, polarity marks, mounting hardware, and special instructions; top and bottom views included with dimensions
Major
Fabrication notes complete
Fab drawing specifies: material, surface finish, copper weights, impedance requirements with tolerance, IPC class, stackup cross-section, and special processes (back-drill, edge plating)
Critical
IPC netlist for bare-board test
IPC-D-356 netlist exported for electrical test; all nets present; net count matches design; test point access provides ≥99% net coverage for flying-probe or fixture test
Major
ODB++ or IPC-2581 package
Intelligent manufacturing data (ODB++ or IPC-2581) exported as single package containing all fabrication and assembly data; validated by importing into fabricator's CAM tool with 0 errors
