All clock harmonics up to 1GHz identified; calculated emission level at 3m is >6dB below Class B limit for each harmonic
Critical
Clock Harmonic Frequencies
Enter a clock frequency to see all harmonic frequencies up to 1 GHz.
Rise/fall time bandwidth
Signal edge rates analyzed using BW = 0.35/t_rise; spectral content above 5th harmonic verified below applicable emission limit with margin
Critical
Current loop area minimization
All high-frequency signal/power loops measured or estimated; loop area reduced such that E-field at 3m < limit minus 10dB margin using E = 1.32e-14 * f^2 * A * I / r
Critical
Spread spectrum clocking
SSC enabled on all clocks >25MHz with 0.5-1.5% modulation depth (center or down-spread); peak reduction verified at >6dB per harmonic
Major
Slew rate control
Driver slew rates set to slowest value that still meets timing margin; calculated BW reduced by at least 2x compared to uncontrolled edge rate
Major
Heatsink grounding
All heatsinks bonded to ground plane or chassis via low-impedance connection (<5mOhm at 100MHz); verified not resonant as patch antenna in 30MHz-1GHz range
Major
Cable common-mode radiation
All cables assessed as monopole antennas; CM chokes applied where cable length is within 0.1-0.5 lambda of any emission frequency; CM current < 5uA at problem frequencies
Critical
Enclosure aperture control
All enclosure openings (ventilation, display, LED) have maximum dimension < lambda/20 at highest emission frequency; waveguide-below-cutoff used for ventilation slots with depth > 3x width
Critical
Seam and gap treatment
Enclosure seams have continuous electrical contact or EMI gaskets with compression providing <20mOhm transfer impedance; slot lengths < lambda/20 at highest frequency of concern
Major
PCB edge radiation
High-speed traces routed >20H (20x dielectric thickness) from PCB plane edges; no clock or periodic signal traces within 2mm of board perimeter
Major
Via fencing at board edges
Ground via fence around board perimeter with via spacing < lambda/20 at highest frequency; vias connect all ground layers and are within 1mm of board edge
Two-stage EMI filter (CM choke + DM inductor + X/Y caps) designed with insertion loss >20dB above switching frequency and harmonics up to 30MHz
Critical
Common-mode choke selection
CM choke impedance >500 Ohm at primary emission frequency; rated current > 1.5x max line current; leakage inductance provides DM filtering
Critical
Differential-mode filter
DM filter (series L + shunt C) provides >40dB attenuation at SMPS fundamental switching frequency; resonant frequency placed below lowest emission frequency
Critical
Filter insertion loss verification
Measured or simulated insertion loss compared against required attenuation (emission level - limit + 6dB margin) at each frequency from 150kHz to 30MHz
Critical
Filter source/load impedance matching
Filter topology (pi, T, L) selected for actual source/load impedances (LISN = 50 Ohm); not relying on 50-Ohm datasheet curves for mismatched environments
Major
X/Y safety capacitor ratings
X-caps rated X1 (4kV) or X2 (2.5kV) per application; Y-caps rated Y1/Y2 per insulation class; total Y-cap leakage <0.5mA for Class II equipment per IEC 60950/62368
Critical
SMPS switching noise containment
Switching regulator conducted noise at fundamental and harmonics measured or estimated >6dB below CISPR 32/EN 55032 limits at LISN; snubber or soft-switching reduces ringing
Critical
Ground loop prevention
No conducted noise coupling path between chassis/earth ground and signal ground at frequencies below 30MHz; single-point or controlled multi-point connection verified
Major
Power line current harmonics
AC input current harmonics from 2nd to 40th order calculated or measured and verified below EN 61000-3-2 Class A/C/D limits for rated power; PFC implemented if required
Major
Voltage fluctuation and flicker
Voltage fluctuation Pst <=1.0 and Plt <=0.65 per EN 61000-3-3; inrush and load-step current profiles verified against standard limits for equipment <=16A
ESD protection verified for +/-8kV contact / +/-15kV air on all user-accessible ports; TVS response time <1ns; clamping voltage below IC absolute max rating
Critical
Radiated immunity (IEC 61000-4-3)
Design verified to operate without degradation under 3-10 V/m RF field (80MHz-6GHz); sensitive analog circuits shielded or bandwidth-limited to reject RF rectification
Critical
EFT/Burst immunity (IEC 61000-4-4)
Power and signal ports withstand +/-2kV (Level 3) fast transient bursts at 5kHz repetition; input filtering provides >40dB attenuation of 5ns/50ns burst waveform
Critical
Surge immunity (IEC 61000-4-5)
Power port withstands +/-2kV L-N and +/-4kV L-PE surge (1.2/50us); MOV/TVS energy rating exceeds 40J for repeated surges; clamping voltage < downstream component abs max
Critical
Conducted RF immunity (IEC 61000-4-6)
All cable ports withstand 3-10 Vrms conducted RF (150kHz-80MHz); decoupling networks placed at cable entry with CM rejection >20dB across band
Major
Power frequency magnetic field
Sensitive circuits (Hall sensors, magnetic media, CRT) immune to 50/60Hz magnetic fields up to 30 A/m (IEC 61000-4-8 Level 4); shielding or orientation verified
Minor
Voltage dips and interruptions
System maintains operation through 30% dip for 500ms and recovers automatically from 100% interruption up to 5s (IEC 61000-4-11); holdup time verified with bulk capacitor sizing
Major
Performance criteria definition
Pass/fail criteria (A/B/C) defined per IEC 61000-6-x for each immunity test; Criterion A = normal operation, B = temporary degradation with self-recovery, C = requires manual restart
Major
Firmware EMI robustness
Software implements watchdog reset, CRC on critical data, communication retries, ADC averaging, and graceful degradation; no permanent hang states from transient-induced bit flips
Overall grounding architecture (single-point, multi-point, or hybrid) documented in design file; transition frequency between topologies defined (typically hybrid above 1MHz)
Critical
Chassis-to-PCB ground bond
PCB ground connected to chassis via low-impedance bond (<2.5mOhm DC, <10mOhm at 100MHz); connection method specified (screw, spring finger, gasket) with defined contact area
Critical
Mixed-signal ground partitioning
Analog and digital ground regions connected at single defined star point beneath ADC/DAC; no digital return current flows through analog ground region
Critical
Ground plane integrity
Solid unbroken ground plane on layer adjacent to every signal layer; no splits, slots, or routing gaps under high-speed traces; plane void area < 5% of total area
Critical
Connector shield grounding
All I/O connector shells bonded to chassis ground via 360-degree contact (not pigtail); bond impedance < 5mOhm from shell to chassis at frequencies up to 1GHz
Critical
Ground stud placement
Chassis ground connection points (studs/lugs) located within 50mm of each I/O connector cluster; mounting hardware uses star washers or serrated flanges for reliable contact
Major
Safety earth continuity
Protective earth path resistance <100mOhm end-to-end per IEC 60950/62368; conductor sized for fault current (typically 18AWG minimum); no fuse/switch in PE path
Critical
Ground bounce management
High-current return paths (motor drivers, relay coils, LED strings) use dedicated ground traces/planes separate from sensitive signal returns; voltage drop < 50mV peak at switching transients
Every I/O line crossing enclosure boundary has EMI filter (ferrite + cap minimum); filter cutoff frequency set below lowest unwanted frequency while passing signal bandwidth with <1dB insertion loss
Critical
Ferrite bead impedance selection
Ferrite beads selected with impedance >100 Ohm at primary noise frequency (verified on manufacturer impedance vs. frequency curve); type chosen for target band (resistive vs. inductive)
Major
Ferrite bead DC bias derating
Ferrite bead operating current verified at <70% of rated saturation current; impedance at bias current still meets requirement (checked from manufacturer DC bias curves)
Major
Pi-filter implementation
Pi-filters (C-L-C) used on power lines requiring >40dB attenuation; component values provide minimum 60dB attenuation at SMPS switching frequency with actual source/load impedances
Major
Common-mode choke for I/O
CM chokes on differential I/O (Ethernet, USB, CAN) provide >30dB CM rejection at EMI frequencies while maintaining <1dB differential insertion loss in signal passband
Major
Feed-through capacitors
Feed-through/bulkhead capacitors used at enclosure penetration points for signals >10MHz; capacitor self-resonant frequency above highest EMI frequency of concern
Major
Snubber circuits for transients
RC snubbers across relay/switch contacts sized to limit dV/dt < 1V/ns; R value damps ringing within 3 cycles; snubber power dissipation within resistor rating at max switching frequency
Major
TVS/varistor selection
TVS breakdown voltage >1.1x max operating; clamping voltage at peak pulse current < protected IC abs max; response time < 1ns for ESD, < 5ns for surge; energy rating > worst-case event energy
Critical
Filter component placement
All EMI filter components placed at board edge within 5mm of connector footprint; filter ground returns directly to connector ground pins with no shared vias; input/output traces physically separated
Required shielding effectiveness (SE) quantified from gap analysis: SE_required = measured_emission - limit + 6dB margin; material and construction selected to meet SE at all frequencies 30MHz-6GHz
Major
Board-level shield cans
On-PCB shields placed over SMPS inductors, oscillators, RF sections, and high-speed clock generators; shield height provides >3mm clearance to tallest component; removable lid for rework access
Major
Shield ground connection
Board-level shields soldered to continuous ground pad ring with no gaps >1mm; ground pad connected to internal ground plane via vias spaced lambda/20 at highest shielded frequency
Critical
Shield aperture control
All openings in shields (ventilation holes, pick-and-place holes) have maximum dimension lambda/20 at highest internal frequency; multiple small holes used instead of single large opening
Major
Cable shielding adequacy
Shielded cables used for all signals >1MHz or sensitive analog; shield coverage >85% braid or foil+drain; transfer impedance 100mOhm/m at highest frequency of concern
Major
Shield termination method
Cable shields terminated via 360-degree clamp or backshell (not pigtail) at both ends; pigtail length zero for frequencies >100MHz; termination impedance < 5mOhm at connector interface
Critical
Compartmentalization
Noisy sections (SMPS, digital logic, motor drivers) physically separated from sensitive sections (analog front-end, RF receiver) by >20dB isolation barrier or minimum 10x wavelength distance
Snap-on or wound CM ferrite chokes placed at enclosure exit on all cables; choke impedance >200 Ohm at dominant CM emission frequency; rated for cable current without saturation
Major
Filtered connector selection
Filtered D-sub or circular connectors with integrated C or pi-filters used where >60dB port-to-port isolation required; filter cutoff below lowest EMI frequency; insertion loss verified per pin
Major
Cable resonance assessment
Cable lengths checked against quarter-wave resonance (lambda/4 = c / 4f) for all emission frequencies; cables that are resonant length fitted with CM suppression or length modified to avoid resonance
Major
Differential signaling for long runs
All signal cables >300mm use differential signaling (RS-485, LVDS, CAN) with >40dB CMRR; single-ended signals on long cables converted to differential with balanced drivers/receivers
Major
Cable routing and separation
Power cables separated from signal cables by minimum 50mm or metal barrier; high-speed cables separated from low-speed by minimum 25mm; crossing at 90 degrees only
Minor
Shield drain wire termination
Drain wire terminated to connector shell or ground lug within 10mm of connector; for frequencies >50MHz, 360-degree braid termination used instead of drain wire; no unterminated shield ends
Noisy components (SMPS, clocks, digital ICs) grouped together and placed far from I/O connectors and sensitive analog; minimum 10mm separation between noisy and sensitive sections with ground stitching boundary
Critical
Return path continuity
Every signal has uninterrupted return path on adjacent reference plane directly beneath the trace; no signal crosses plane split without stitching capacitor or bridge; return path verified in layout tool
Critical
20H rule for power planes
Power plane edges set back from ground plane edges by minimum 20x dielectric thickness (20H); reduces fringing fields and edge radiation by >10dB above 500MHz
Major
No high-speed traces at board edge
All traces with edge rates < 2ns routed at least 3x trace width from board edge; clock traces routed minimum 5mm from any board edge to prevent edge-fired radiation
Major
Clock trace routing minimized
Clock trace lengths minimized to absolute required distance; no stubs or unnecessary meanders; clock routed on internal layers between ground planes for maximum shielding
Major
Decoupling capacitor placement
Decoupling caps placed within 2mm of IC power pins with via-in-pad or adjacent via to ground plane; loop area (pad-to-via-to-plane) minimized to <4mm^2; no shared vias between caps
Critical
Ground stitching vias
Ground stitching vias placed between functional zones at spacing < lambda/20 at highest frequency; via fence around sensitive circuits provides >20dB isolation from adjacent noisy regions
Major
Slot antenna avoidance
No narrow slots (length > lambda/2) in ground plane created by via rows, connector cutouts, or trace gaps; any necessary slots bridged with stitching vias at
Critical
Crystal/oscillator isolation
Crystal oscillator circuits placed >15mm from I/O connectors and board edges; local ground guard ring with stitching vias surrounds oscillator; no other traces routed within 3mm of crystal
Complete list of required EMC standards documented (FCC Part 15, CISPR 32, EN 55032/55035, MIL-STD-461G, automotive CISPR 25) based on product type, market, and intended environment
Critical
Class A vs. Class B classification
Product correctly classified as Class B (residential) or Class A (commercial/industrial); Class B limits applied if product may be used in domestic environment; classification documented with rationale
Critical
Pre-compliance test plan
Pre-compliance test plan covers all required emissions and immunity tests; scheduled before PCB fabrication commitment; includes near-field probe scanning, GTEM cell, or open-area approximation
Major
Design margin targets
Design targets set at limit minus 6dB minimum for emissions and limit plus 6dB for immunity; critical frequencies (clock harmonics, switching frequency) targeted at limit minus 10dB
Major
Test configuration defined
Worst-case test configuration documented: all cables attached at maximum length, all ports loaded, highest clock mode active, all peripherals operating; matches conditions required by test standard
Major
EMI mitigation contingency
Backup mitigation features designed in: unpopulated ferrite bead pads on I/O, shield can footprints on PCB, space for snap-on cable ferrites, gasket grooves in enclosure; minimum 3 mitigation options per identified risk
Major
Safety certification compliance
Product safety standards (IEC 62368-1, IEC 60601-1, IEC 61010-1) identified and designed for; creepage/clearance distances meet requirements; insulation coordination documented per applicable standard
Critical
Wireless coexistence
If product contains wireless (WiFi, BT, cellular, Zigbee), desense analysis performed showing on-board noise floor at antenna < -90dBm across receive band; antenna placement >10mm from digital ICs and SMPS
