Module 4.8 - PCB-Level EMC Design
Design review checkpoints for PCB layout techniques that minimize electromagnetic interference at the board level
Design review checkpoints for PCB layout techniques that minimize electromagnetic interference at the board level
The "20H rule" states that the power plane should be set back (pulled in) from the ground plane edge by a distance equal to 20 times the dielectric spacing between the planes. This reduces fringing electric fields at the board edge that cause radiation from the power-ground plane cavity.
4-layer board with proper 20H setback: GND-PWR core thickness: 0.2mm. Power plane pulled back 4mm from all edges. Ground plane extends to board edge (provides shielding at edge). Perimeter stitching vias connecting top and bottom ground pours at 10mm spacing. Near-field scan shows 8 dB reduction in edge radiation at 500 MHz compared to flush power plane. Decoupling capacitors placed at the power plane edge (where current density is highest after setback) for additional benefit.
Power plane extending to board edge: Power and ground planes both extend to the board edge. The 0.2mm gap between planes at the edge acts as a slot antenna driven by switching noise in the cavity. At the board cavity resonance (measured: 520 MHz for 150mm board), edge radiation peaks -- 18 dBuV/m measured at 3m. This single radiation mechanism causes FCC Class B failure by 5 dB at 520 MHz.
Setback creates routing challenge: The setback zone has no power plane, so components near the board edge must be fed by power traces instead of direct plane connection. This increases impedance to edge components and can cause power integrity issues. Solution: Use wider power traces (20+ mil) with local decoupling at each edge component.
20H rule alone is insufficient: The 20H rule should be combined with (not substituted for) proper decoupling, stitching vias, and layout practices. It is one tool in the toolbox, not a complete solution.
Stitching vias around the PCB perimeter connect ground layers together, creating a Faraday cage effect that reduces edge radiation. The via spacing must be less than lambda/20 at the highest frequency of concern to prevent slot antenna effects between vias. This is one of the most effective PCB-level EMC techniques.
| Via Spacing | Effective To | Application | Via Count (100x100mm board) |
|---|---|---|---|
| 15 mm | 500 MHz | General digital (100 MHz clocks) | 27 |
| 10 mm | 800 MHz | Fast digital (200+ MHz clocks) | 40 |
| 5 mm | 1.6 GHz | High-speed digital (USB 3.0, DDR4) | 80 |
| 2.5 mm | 3.2 GHz | Very high-speed (PCIe Gen3/4, 10GbE) | 160 |
| 1.5 mm | 5.3 GHz | RF/mmWave, 5G applications | 267 |
6-layer board with comprehensive via stitching: Board hosts DDR4-3200 memory (1.6 GHz fundamental). Via stitching at 4mm spacing around entire perimeter (100 vias for 200x100mm board). Additional via fences around DDR4 routing channel (3mm spacing) and clock generator area (2.5mm spacing). Ground pour on top and bottom layers connects all stitching vias. Measured edge radiation reduction: 15 dB at 1.6 GHz compared to board without stitching. Passes CISPR 32 Class B with 8 dB margin.
Board with sporadic ground vias, no perimeter fence: Ground vias placed only where needed for component connections, approximately 30-50mm apart at board edges. No intentional perimeter stitching. At 1 GHz, the 40mm gap between ground vias acts as a slot antenna. Board edge radiation at 1 GHz: 15 dB higher than properly stitched board. The 40mm slot resonates near 3.75 GHz (half-wave), creating additional emission peak.
PCB CAD Implementation: Most PCB tools support "via fence" or "via stitching" features that automatically place vias at specified spacing along a defined path. In Altium: Place > Via Stitching. In Cadence Allegro: Route > Create Fanout > Via Array. In KiCad: Use scripting plugin for via fence. Define the fence as a design rule so it persists through design changes.
When a signal trace crosses a split (gap) in its reference plane, the return current must find an alternate path around the split. This creates a large current loop that acts as an efficient radiating antenna. This is one of the most common and severe PCB EMC design errors.
Mixed-signal board with no split crossings: Board has analog and digital ground regions separated by a narrow split. All digital signals route within the digital region. All analog signals route within the analog region. The ONLY signal crossing the boundary is the ADC data bus, which crosses directly over the bridge point (2mm wide copper connection under the ADC). Every other signal stays within its region. Return-path simulation confirms all return currents flow under their respective traces with no detours.
Clock trace crossing power plane split: 100 MHz clock trace routes on Layer 1, referenced to Layer 2 ground plane. But Layer 2 has a split for separate analog power domain, and the clock trace crosses this split for 15mm. Return current must detour 40mm around the split. Additional loop area: 40mm * 0.15mm = 6 mm^2. At 300 MHz (3rd harmonic): radiated field increases by 12 dB. This single trace crossing is responsible for a CISPR 32 Class B failure at 300 MHz. Fix: reroute clock trace to stay within continuous ground region.
Via anti-pad clearances creating "mini-splits": Dense via fields (under BGA packages) can remove so much copper from the reference plane that the plane becomes essentially discontinuous. A signal trace routing through a via field may have no continuous reference plane beneath it. Solution: Use via-in-pad technology to reduce anti-pad size, or route signals on layers with continuous (unperforated) reference planes.
Power plane used as reference: Many signals use a power plane (not ground) as their return path reference. If the power plane has splits (for multiple voltages), these splits have the same effect as ground plane splits on signal return currents. Verify that signals referenced to power planes don't cross voltage domain boundaries.
Component placement significantly affects EMC performance. Noisy components (high-speed processors, clock generators, switch-mode regulators) should be placed away from board edges and cable connectors to minimize radiation coupling. Sensitive components (analog front-ends, receivers) should be isolated from noise sources.
Well-zoned PCB layout: North edge: all I/O connectors (USB, Ethernet, HDMI, power jack) with EMI filters within 5mm. Center: FPGA and DDR4 memory with clock generator in the middle (maximum distance from all edges). South-west corner: switching regulators (noise contained by local stitching via fence). South-east corner: analog sensor interface (isolated from digital by via fence and ground moat bridge). No high-speed signals route to board edges. Near-field scan confirms noise concentration at center with clean edges.
Clock generator at board edge near USB connector: 100 MHz crystal oscillator placed 3mm from board edge, 10mm from USB connector. Clock harmonics couple directly to USB cable through near-field coupling and edge radiation. The USB cable, acting as an antenna at 300 MHz (3rd harmonic), radiates the clock noise efficiently. Moving the oscillator to board center (40mm from edge) would reduce edge coupling by 20 dB and cable coupling by similar amount.
When a signal transitions from one layer to another via a through-hole via, its return current must also transition between reference planes. If no nearby ground stitching via provides this path, the return current must find an alternate route, creating a large loop area that radiates. Every signal via MUST have an adjacent ground stitching via.
DDR4 data byte lane with stitching vias: 8 DDR4 data signals transition from Layer 1 to Layer 3 as a group. 4 ground stitching vias placed within the via field (one per 2 signals), connecting Layer 2 GND and Layer 4 GND. Stitching via distance from nearest signal via: 0.7 mm maximum. Return current simulation shows clean transition with no current spreading. TDR measurement shows less than 2 ohm impedance discontinuity at the via transition.
Clock signal via with no stitching: 200 MHz clock transitions from Layer 1 (ref Layer 2 GND) to Layer 6 (ref Layer 5 GND). No ground stitching via within 8mm (nearest ground via is a component mounting via 8mm away). Return current must spread 8mm to find a path between L2 GND and L5 GND. Loop area: approximately 8mm * 1.2mm (stackup height) = 9.6 mm^2. At 600 MHz (3rd harmonic): this loop radiates 18 dB more than a properly stitched transition. The single missing stitching via causes a 600 MHz emission peak that fails FCC by 6 dB.
Verification in PCB Tool: Use Design Rule Checks (DRC) to verify stitching via proximity. In Altium: Create a "Return Via" rule that flags signal vias without a ground via within specified distance. In Cadence: Use Constraint Manager to define via-to-via spacing requirements. Some tools (HyperLynx, Ansys SIwave) can visualize return current paths and identify violations.
A guard ring is a grounded copper trace or pour that surrounds sensitive analog circuits to shield them from digital noise coupling through the PCB substrate and surface. Guard rings are particularly important for high-impedance nodes, precision references, and low-level sensor inputs where even picoamps of leakage or microvolts of coupled noise affect performance.
24-bit ADC with complete guard ring: ADC analog input section (4 differential channels + reference) enclosed in a 2mm wide grounded copper ring on Layer 1. Ring connected to analog ground plane (Layer 2) with 24 vias at 3mm spacing. Layer 2 is solid ground plane under the entire guarded area -- no vias, no routing. Layer 3 has copper keep-out zone matching the guarded area. Digital signals from ADC SPI bus exit through a single designated gap in the ring (with ferrite beads in series). Measured noise floor: 0.8 uVrms (achieves 20.5 ENOB). Without guard ring: noise floor was 3.2 uVrms (18.5 ENOB).
Guard ring with gap and no stitching: Guard ring drawn around precision amplifier but with a 5mm gap where a power trace crosses into the ring. Ring has only 2 ground vias (one at each end where it was drawn). The gap allows digital noise to couple through the opening. The sparse vias mean the ring is not connected to ground at high frequencies (inductance too high). At 200 MHz: ring has 30 ohm impedance to ground via its 2 vias -- provides no shielding benefit. The gap creates a slot that may actually FOCUS digital noise into the sensitive area.
Guard ring connected to wrong ground: If the guard ring connects to noisy digital ground instead of quiet analog ground, it injects noise directly into the sensitive area rather than shielding it. Always verify the guard ring connects to the same ground reference as the sensitive circuit it protects.
Thermal relief pads on guard ring vias: Thermal relief patterns on guard ring via pads reduce the connection width, increasing inductance at high frequencies. Use direct (no thermal relief) connections for guard ring vias to maximize RF ground integrity.