Module 3: Power Integrity (PI)

Z_target = (Vdd × ripple%) / I_transient calculated for every rail; PDN impedance meets target from DC to 1 GHz

PDN impedance remains below Z_target from DC through the highest transient frequency (f_knee = 0.35/t_rise); no gaps in coverage

No resonant peaks in PDN impedance profile exceed Z_target; Q-factor of any resonance < 2 across entire frequency range

Parallel resonance peaks between adjacent capacitor values damped to < Z_target using ESR selection or resistive damping; no peak > 1.5x Z_target

VRM output impedance characterized from DC to bandwidth limit; VRM Z_out included in PDN model and remains below Z_target up to its control-loop crossover frequency

Total noise budget partitioned: VRM ripple ≤ 30% of rail tolerance, PDN resonance ≤ 40%, SSN ≤ 30%; sum of all contributions < IC specified max ripple

PDN meets IC vendor-specified impedance at stated frequencies (e.g., FPGA power integrity guidelines); verification data documented per rail

SSN voltage = L_eff × (N_outputs × I_switch / t_rise) calculated for worst-case bus switching; result < 50% of noise margin for the I/O standard

Total voltage variation (DC drop + AC ripple + transient undershoot) keeps rail within IC min/max operating voltage at the die; margin ≥ 5% on each side

Minimum 3 decade-spaced values selected (e.g., 10 uF, 1 uF, 100 nF, 10 nF) to cover VRM bandwidth to SRF of smallest cap; each value's SRF overlaps next value's effective range

Number of decoupling caps per IC meets or exceeds datasheet recommendation; total mounted capacitance at operating voltage delivers required charge (Q = C_eff × delta_V ≥ I_transient × t_response)

High-frequency caps (100 nF and below) placed within 1 mm of IC power pin via; mid-frequency caps within 5 mm; bulk caps within 15 mm of IC boundary

Each cap pad connects to power/ground plane with ≥ 2 vias per pad; via-to-pad trace length < 0.5 mm; total loop inductance < 0.5 nH per cap

Total mounted inductance (ESL + pad + via + trace) < 0.3 nH for 0402 body size; via-in-pad or reverse-geometry caps used for frequencies > 200 MHz

Self-resonant frequency of each cap value verified from vendor impedance curves; SRF aligns with target frequency band within 0.5 decade; caps ineffective above SRF not relied upon

Decoupling cap effective capacitance at DC bias checked from vendor curves; actual capacitance > 50% of nominal at operating voltage; design accounts for derated value

Capacitance variation over full operating temperature range documented; X7R: ≤ ±15% over -55 to +125 C; X5R: ≤ ±15% over -55 to +85 C; worst-case value used in PDN model

Bulk cap ESR selected to provide damping at mid-frequency (1-10 MHz) anti-resonance; ESR × C product produces Q < 2 at resonant peaks between bulk and MLCC

Thin-core plane pairs (< 50 um dielectric) evaluated for high-frequency decoupling above 100 MHz; embedded capacitance per unit area calculated and included in PDN model if used

Each voltage domain with > 1 A load has a dedicated plane or pour; power-ground plane pairs placed on adjacent layers with dielectric ≤ 100 um for interplane capacitance

Ground plane is continuous (no splits or slots) under all ICs and high-speed signal routing; any necessary split bridged with stitching caps at ≤ 5 mm spacing

Power plane copper area yields current density ≤ 35 A/mm2 for internal layers (per IPC-2152); no necked-down regions reducing effective width below required value

Power-ground plane pair spacing ≤ 75 um (3 mil) for maximum interplane capacitance; provides > 20 pF/cm2 embedded capacitance for high-frequency decoupling

No high-speed signal crosses a power plane boundary without a continuous return path; signals crossing splits have adjacent ground stitching vias within 1 mm

Ground planes on different layers stitched with vias at ≤ lambda/20 spacing (e.g., ≤ 7.5 mm for 2 GHz); stitching vias placed around board perimeter and near IC clusters

Plane cavity resonance frequencies calculated (f_mn = c/(2*sqrt(er)) * sqrt((m/a)^2+(n/b)^2)); resonances near switching frequencies damped with distributed decaps or lossy dielectric

Copper density balanced within ±15% across all layers (fill patterns added where needed); prevents bow/twist > 0.75% per IPC-6012 Class 2/3

High-current connections (> 1 A) use direct-connect (no thermal relief) to plane; low-current connections use thermal relief with 4 spokes ≥ 0.25 mm wide for solderability

DRC confirms zero floating copper islands on any layer; all copper pours connected to a net with verified via connections; isolated fills removed or stitched

Regulator output voltage within ±1% of target (or IC specified tolerance) over full load range (0 to I_max) and temperature range (-40 to +85 C minimum)

Output voltage change from 10% load to 100% load ≤ 1% of nominal (or per regulator datasheet spec); measured at IC power pins, not regulator output

Output voltage variation ≤ 0.5% over full input voltage range (V_in_min to V_in_max); verified at typical and maximum load conditions

Converter efficiency ≥ 85% at typical load (or as required by thermal budget); power loss (P_in - P_out) verified to be dissipatable without exceeding T_j_max at max ambient

Inductance within ±20% of design calculation; I_sat > 1.3 × I_peak at max temp; DCR contributes < 2% efficiency loss at full load; no audible magnetostriction at operating frequency

Output capacitance meets transient requirement: C_out ≥ I_step × t_response / delta_V_allowed; ESR within regulator stability range; ripple current rating > I_ripple_RMS

Input capacitance handles RMS ripple current: I_rms = I_out × sqrt(D × (1-D)) for buck; cap ripple current rating > calculated I_rms × 1.2; ESR low enough to limit input voltage ripple

Soft-start time configured so inrush current < input source/fuse rating; ramp rate meets downstream IC requirements (if specified); SS capacitor value matches target ramp time ±20%

Current limit set to: I_limit > I_max_load × 1.2 AND I_limit < minimum of (inductor I_sat, trace capacity, downstream component rating); hiccup/latch-off mode selected appropriately

Regulator junction temperature at max ambient and full load: T_j = T_a + (theta_JA × P_diss) < T_shutdown - 20 C; thermal shutdown threshold verified against calculated worst-case T_j

Switch node loop area < 2 cm2; input cap within 3 mm of VIN/GND pins; feedback sense trace routed away from switch node; ground star point follows datasheet recommendation

Bootstrap cap value per datasheet (typically 100 nF); snubber RC sized to damp switch node ringing below 80% of FET V_ds_max; component power dissipation within rating

Power-up sequence documented and verified against every IC datasheet requirement (core before I/O, VCCINT before VCCAUX, etc.); no IC sees I/O voltage before core is stable

Voltage ramp rates within IC specifications: minimum ramp rate met (prevents indefinite intermediate state) and maximum ramp rate not exceeded (prevents latch-up); measured dV/dt documented

Power-down sequence reverse of power-up (or per IC requirement); no rail remains powered that could cause current injection into unpowered IC; verified with scope capture

Supply voltages rise monotonically from 0 V to final value with no dips > 100 mV; pre-bias safe operation verified if output cap pre-charged from other rails

Power sequencer enable/PGOOD chain connections match design intent; timing registers/resistors configured for correct delays (tolerance ±10%); fault response bits set correctly

Behavior specified for each fault type: overcurrent (latch-off vs. hiccup), PGOOD timeout (retry count), thermal (shutdown + hysteresis); fault flags readable by system controller

Hot-swap controller limits inrush to < connector pin current rating; FET SOA not exceeded during insertion; output reaches regulation within specified time; no downstream voltage overshoot

Power mux/ORing switchover time < load hold-up time (C_hold × delta_V / I_load); no output voltage dip > 5% during transition; reverse current blocking verified

Low-power mode disables non-essential rails; always-on rails maintain state with quiescent current < budget (e.g., < 10 uA for battery-powered); wake-up time from sleep meets system requirement

Trace widths calculated per IPC-2152 for ≤ 10 C temperature rise at maximum current; internal layers derated by 50% vs. external; calculations documented for each power trace

Number of vias × per-via current capacity (typically 0.5-1 A per 0.3 mm via) exceeds maximum trace current × 1.5; via thermal rise < 10 C above trace temperature

Multiple connector pins allocated for currents > single-pin rating; total pin count provides ≥ 50% derating (e.g., 4 pins rated 1 A each for a 2 A load); pin resistance mismatch < 10%

No current crowding hot spots exceed 50 A/mm2 for 1 oz copper (internal) in DC analysis; bottleneck regions identified and widened or reinforced with additional vias/layers

DC IR drop from regulator output to farthest IC pin < 1% of rail voltage (or within rail tolerance budget); IR drop simulation performed and worst-case pin voltage > IC V_min

Downstream protection trips before upstream for selective coordination; I2t clearing energy of downstream fuse < I2t withstand of upstream fuse at all fault levels

Remote voltage sense lines routed as Kelvin connection directly to load point; sense traces carry < 1 mA (no significant IR drop); sense lines filtered with 100 nF cap at regulator

Copper weight selected for current requirements: 1 oz (35 um) for ≤ 3 A traces, 2 oz (70 um) for 3-6 A, heavier for higher; inner vs. outer layer capability confirmed with fabricator

Voltage undershoot/overshoot during worst-case load step (0 to I_max in < 1 us) remains within IC supply tolerance; delta_V < C_out × ESR × di/dt + I_step / (C_out × BW)

Regulator settles to within ±1% of nominal within 50 us (or application-specified time) after load transient; no sustained ringing or oscillation > 3 cycles

Maximum di/dt event identified (e.g., processor burst mode, DDR training, radio TX burst); magnitude = N_gates × I_per_gate / t_rise; PDN response simulated for this specific event

Phase margin > 45 degrees and gain margin > 10 dB verified by simulation or measurement across full load and temperature range; crossover frequency < 1/5 of switching frequency

Closed-loop output impedance (|Z_out|) has no peaking > 2x the low-frequency value near crossover; peaking indicates insufficient phase margin; verified with impedance plot

Electrolytic/polymer cap capacitance derated 20% for end-of-life aging; transient response re-verified with aged capacitor values; design meets spec at both BOL and EOL

IR drop analysis performed for all power nets at maximum load; voltage at every IC power pin confirmed > IC V_min; worst-case voltage drop map documented with values in mV

Frequency-domain PDN impedance simulated from 1 kHz to 1 GHz; impedance plot overlaid with Z_target curve; all frequency bands below target confirmed; simulation includes package model

Current density simulation identifies all bottlenecks with J > 30 A/mm2 (1 oz internal); hot spots resolved by widening traces, adding vias, or distributing current across multiple paths

Cavity resonance modes calculated and simulated; any resonance within 2x of clock/switching frequency identified; damping added (distributed caps, lossy material) to reduce Q below 5

Capacitor placement optimized through iterative simulation (value, quantity, location); final design achieves Z_target with minimum component count; sensitivity analysis identifies critical caps

Combined PI-SI simulation captures PDN noise impact on signal eye diagram; eye height reduction due to supply noise < 10% of total eye budget; jitter contribution from PDN noise quantified

Simulation results correlated with bench measurements on prototype; measured vs. simulated impedance within ±30% up to 500 MHz; discrepancies explained and model updated