Tutorial: Module 3.5 - Power Sequencing & Control

Checkpoint 1: Power Sequence Matches IC Requirements Critical

Many complex ICs (FPGAs, processors, DDR memory, SerDes devices) have strict power-up sequencing requirements. Violating the sequence can cause latch-up (potentially destructive), excessive current draw during startup, ESD protection diode forward-biasing, or device malfunction. The sequence must be determined from IC datasheets and enforced by hardware.

Common Sequencing Requirements

IC Type	Typical Sequence	Timing Requirement
Xilinx UltraScale+ FPGA	VCCINT -> VCCAUX -> VCCIO -> VCCO_DDR	Each rail within 20ms of previous
Intel/Altera Stratix 10	VCC -> VCCERAM -> VCCT/R -> VCCIO	100us min between stages
DDR4 SDRAM	VDD -> VDDQ -> VPP (simultaneously OK)	VPP must not exceed VDD+0.3V
TI Sitara AM57x	VDD_CORE -> VDD_MPU -> VDD_IO -> VDDS_DDR	Ramp rate 0.1-15 mV/us
Ethernet PHY (88E1512)	AVDD1.0 -> DVDD1.0 -> VDD3.3 or simultaneous	Delta < 200ms between rails

How to Determine Sequencing Requirements

Read the IC datasheet "Power Supply" or "Power Sequencing" section completely.
Look for absolute maximum ratings: Vpin <= VDDIO + 0.3V (indicates I/O needs power before signals).
Check for explicit sequence diagrams in the datasheet or hardware design guide.
For FPGAs: Check the Power Management user guide (separate document from datasheet).
For processors: Check the Hardware Design Guide and Power Reference Design.
Document the complete sequence with timing in a power-on timing diagram.
Design hardware to enforce the sequence (see sequencer IC selection below).

Sequencing Implementation Methods

Resistor divider on EN pins: Simplest method. Use regulator PG (power-good) output to enable next stage via resistor divider threshold on EN pin.
Dedicated sequencer IC: TPS65xxx series, UCD9090, LTC2924 provide programmable multi-rail sequencing.
PMIC (Power Management IC): Integrated solution with all regulators + sequencing in one device (e.g., TPS65910, PMIC for Zynq).
CPLD/Microcontroller: Maximum flexibility for complex sequences with conditional logic.

Xilinx Zynq-7000 proper sequencing (TPS65xxx PMIC):
Sequence programmed in TPS65217C:
1. VCC_INT (1.0V) -- enable immediately, PG delay 2ms
2. VCC_AUX (1.8V) -- enabled by VCC_INT PG, PG delay 2ms
3. VCC_IO (3.3V) -- enabled by VCC_AUX PG, PG delay 2ms
4. VCC_DDR (1.35V) -- enabled by VCC_IO PG, PG delay 5ms
5. PS_POR_B deasserted 100ms after all PG valid
Total startup time: ~111ms (well within user expectations)
All rails monotonically rising. Sequence matches Zynq-7000 requirements exactly.

FPGA I/O powered before core (latch-up risk):
VCC_IO (3.3V) comes up first because it uses an always-on LDO from 5V input.
VCC_INT (1.0V) takes 15ms longer to start due to buck soft-start.
During this 15ms window:
- I/O pins have 3.3V applied with no core voltage
- ESD clamp diodes forward-bias from I/O pads to core supply
- Parasitic SCR structures can trigger (latch-up)
- Measured current during this window: 2.5A on VCC_IO (should be < 100mA)
Result: 3% of boards latch-up during power-on and require power cycle.

Assuming simultaneous is always safe: Even "simultaneous" rails may have 100us skew due to different soft-start times. Verify worst-case overlap.
Not considering PG propagation delay: A PG signal may have 50-200us delay after the rail reaches regulation. Factor this into timing.
Ignoring power-down sequence: Many ICs also specify power-down order (often reverse of power-up). This is frequently overlooked.
External I/O signals before I/O power: If a cable connects to a powered external device, I/O pins may see voltage before VCC_IO is stable.

Checkpoint 2: Ramp Rate Within Specification Major

The ramp rate (dV/dt) of each power rail during startup must be within the IC's specified range. Too fast a ramp can cause excessive inrush current and trigger protection circuits. Too slow a ramp can leave the IC in an indeterminate state for an extended period, causing unpredictable behavior.

Ramp Rate Calculation

Ramp rate = V_final / t_rise

For a regulator with soft-start:
t_rise = t_softstart (from datasheet or external SS capacitor)

External soft-start timing (TPS54331):
t_ss = C_ss * V_ref / I_ss
Where I_ss = soft-start charge current (typically 2-10 uA)

Example: V_out = 3.3V, V_ref = 0.8V, I_ss = 2.4uA, C_ss = 47nF
t_ss = 47e-9 * 0.8 / 2.4e-6 = 15.7ms
Ramp rate = 3.3V / 15.7ms = 0.21 mV/us

Common specifications:
- Xilinx UltraScale+: 0.2 - 50 mV/us
- DDR4: 0.3 - 15 mV/us (JEDEC JESD79-4)
- Intel processors: 0.25 - 10 mV/us

Controlling Ramp Rate

Calculate natural ramp rate from regulator soft-start time and output voltage.
Compare against IC requirements (both minimum and maximum).
If too fast: Increase soft-start capacitor (C_ss) to slow down ramp.
If too slow: Decrease soft-start capacitor, or use a faster-responding regulator.
Verify ramp rate with oscilloscope during board bring-up (measure 10% to 90% points).
Check ramp rate under all load conditions (loaded vs. unloaded may differ).

Soft-Start Capacitor Sizing

Target ramp rate: 1 mV/us (for FPGA core rail, 1.0V)
Required t_rise = V_out / ramp_rate = 1.0V / 1e-3 V/us = 1ms

For TPS62130 (internal soft-start adjustable via external cap):
t_ss = C_ss * 0.6V / 5uA
C_ss = t_ss * 5uA / 0.6V = 1e-3 * 5e-6 / 0.6 = 8.3nF
Select: 10nF (standard value) -- gives t_ss = 1.2ms, rate = 0.83 mV/us

For UCD9090 sequencer (programmable via I2C):
Ramp rate configured in 0.25 mV/us steps from 0.25 to 12.75 mV/us
Set register VOUT_TRANSITION_RATE = 0x04 for 1.0 mV/us

DDR4 VDD ramp meeting JEDEC spec:
Requirement: 0.3 to 15 mV/us ramp rate for VDD (1.2V)
Regulator: TPS51200 DDR termination regulator with 10nF soft-start cap
t_rise = 10e-9 * 0.5V / 3uA = 1.67ms
Ramp rate = 1.2V / 1.67ms = 0.72 mV/us (within 0.3-15 mV/us spec)
Measured: 0.68 mV/us (agrees with calculation within 6%)

Ramp too fast for FPGA (inrush current issue):
TPS62130 with no external soft-start cap (internal only, ~300us):
Ramp rate = 1.0V / 300us = 3.3 mV/us (within FPGA spec of 0.2-50)
BUT: Inrush current = C_total * dV/dt = 500uF * 3.3e3 = 1.65A inrush!
This exceeds the input supply's current limit (1A fuse).
Fuse blows during power-up. Increase soft-start to 5ms minimum.

Not considering load capacitance on ramp rate: Large output capacitance can slow the effective ramp rate as the regulator current-limits during startup.
Pre-biased startup: If a rail has residual voltage from a previous power cycle, the regulator must handle pre-bias without discharging and re-ramping (causes non-monotonic rise).
Different ramp rates at different temperatures: Soft-start current may vary with temperature, changing the ramp rate. Verify at temperature extremes.

Checkpoint 3: Monotonic Rise Guaranteed Critical

A monotonic rise means the voltage only increases during power-up -- it never dips or reverses direction. Non-monotonic behavior can cause the IC to enter an unpredictable state, fail to initialize properly, or trigger internal power-on-reset circuits multiple times leading to unreliable startup.

Causes of Non-Monotonic Rise

Output capacitor pre-charge: Leakage through body diodes or feedback resistors creates a small initial charge. When the regulator enables, it may pull down momentarily before ramping up.
Interaction between rails: One rail enabling causes a transient disturbance on another rail through ground bounce or coupling.
VRM hiccup mode: Overcurrent protection triggering during startup causes the rail to ramp, trip, reset, and ramp again.
Input voltage sag: Multiple regulators enabling simultaneously causes input supply to droop, briefly dropping all outputs.
Load current spike: IC begins drawing current before rail is fully up, causing voltage to dip.

How to Verify Monotonic Rise

Set oscilloscope to single-shot trigger on the power supply enable signal.
Capture the complete power-up waveform from 0V to final voltage at 1ms/div or slower.
Zoom in on any suspicious dips or plateaus in the waveform.
Verify no voltage reversal exceeds 50mV (or IC-specific threshold).
Test under multiple conditions: cold start, warm start (quick power cycle), with/without load.
Test with minimum and maximum input voltage (affects soft-start behavior).

Ensuring Monotonic Rise

Anti-backflow protection for pre-bias:
Many modern regulators have "pre-bias safe" or "monotonic startup" feature.

Regulators with pre-bias protection (will NOT discharge output):
- TPS62130: Yes (inherent in architecture)
- TPS54331: Yes (uses soft-start to ramp from any initial voltage)
- LTC3018: Yes (pre-biased startup mode)

Regulators WITHOUT pre-bias protection (will discharge to 0V first):
- LM1117: No (will pull output to GND via pass element body diode)
- Some LDOs with active discharge

For non-pre-bias-safe regulators, add series Schottky diode or MOSFET
to prevent reverse current from output to regulator.

Monotonic rise verified on all 6 rails:
Board with TPS65263 triple buck + TPS7A4901 LDO:
All rails show clean monotonic ramp:
- VCCINT: 0 -> 1.0V in 2.1ms, no dips > 5mV
- VCCAUX: 0 -> 1.8V in 2.3ms, no dips > 3mV
- VCC3.3: 0 -> 3.3V in 3.1ms, no dips
- VCC_DDR: 0 -> 1.35V in 1.8ms, no dips
Staggered enable ensures no input supply sag.
Pre-bias safe regulators handle hot-swap reconnection without non-monotonic behavior.

Non-monotonic rise causing FPGA config failure:
VCCINT ramps to 0.6V, then dips to 0.4V for 200us, then continues to 1.0V.
Cause: Three regulators enable simultaneously, input 12V supply droops from 12V to 9.5V for 200us.
The 12V droop causes all buck outputs to sag proportionally.
FPGA sees VCCINT cross its POR threshold twice -- double reset.
Configuration state machine enters unknown state -- requires full power cycle.
Fix: Stagger enables with 5ms gaps. Or add larger input capacitance (bulk storage).

Checkpoint 4: Power-Good Signals Validated Major

Power-Good (PG) signals indicate when a voltage rail has reached its regulation target and is stable. These signals are used to sequence subsequent rails, release device reset signals, and signal system health to monitoring circuits. Every critical rail should have a PG output that is properly debounced and routed to the appropriate consumer.

PG Signal Characteristics

Typical PG behavior:
- Output: Open-drain (requires external pull-up resistor)
- Assert threshold: V_out >= 90-95% of regulation target
- Deassert threshold: V_out < 85-90% of regulation target
- Assert delay: 50-500us after threshold crossing (internal filter)
- Pull-up resistor: 10k-100k to appropriate logic voltage

Pull-up resistor calculation:
R_pullup = V_logic / I_sink_max
I_sink_max for open-drain PG: typically 1-5 mA

Example: PG drives 3.3V logic, I_sink = 1mA max:
R_pullup(min) = 3.3V / 1mA = 3.3k (choose 10k for lower power)
Rise time = R_pullup * C_load = 10k * 10pF = 100ns (fast enough)

PG Signal Validation Checklist

Verify each regulator PG output has a pull-up resistor to the correct voltage domain.
Confirm PG pull-up voltage is from a rail that is stable BEFORE the monitored rail (chicken-and-egg problem).
Check PG routing does not pass through unpowered logic (buffer ICs that are off will block PG).
Verify PG assert delay is adequate (rail must be truly stable before signaling OK).
Test PG deassert behavior: must deassert before V_out drops below IC minimum operating voltage.
For cascaded sequencing: verify total PG chain delay fits within startup time budget.

Proper PG cascade for 4-rail system:
Rail 1 (1.0V Core) PG -> enables Rail 2 (1.8V Aux) via EN pin
Rail 2 (1.8V Aux) PG -> enables Rail 3 (3.3V I/O) via EN pin
Rail 3 (3.3V I/O) PG -> enables Rail 4 (DDR 1.35V) via EN pin
Rail 4 PG -> releases FPGA POR (active-low) after 100ms RC delay

Each PG has 10k pull-up to its own rail (valid because each rail is up before needed).
Total startup time: 4 * (soft-start + PG delay) = 4 * (3ms + 0.2ms) = 12.8ms + 100ms POR = 113ms

PG pull-up to unpowered rail:
Rail 1 (1.0V) PG has pull-up to 3.3V rail, but 3.3V comes up AFTER 1.0V.
During startup: PG pin floats (no pull-up voltage available).
Downstream enable pins see indeterminate voltage -- may glitch.
Rail 2 may false-start, violating sequence.
Fix: Pull up to the rail being monitored, or to an always-on supply.

Missing pull-up on PG: Open-drain outputs float high-Z when deasserted. Without pull-up, downstream logic sees undefined state.
PG connected to voltage-sensitive input: If PG drives an IC input that cannot tolerate voltage above its own supply, damage can occur if PG pull-up voltage exceeds VCC of that IC.
No PG on critical rail: Some regulators lack PG output. Must add external voltage supervisor (TPS3839, MAX6746) for monitoring.
Glitch on PG during transients: A brief load transient can momentarily deassert PG, triggering false shutdown. Add RC filter or use PG with built-in deglitch.

Checkpoint 5: Enable Pin Timing Margins Major

The enable (EN) pin of each regulator has specific voltage thresholds and timing requirements. Proper margin between the actual EN voltage and the threshold ensures reliable startup regardless of component tolerance, temperature, and noise on the enable line.

Enable Threshold Analysis

Typical EN pin specifications (TPS62130 example):
- EN rising threshold (V_EN_H): 1.0V typical (0.9V min, 1.15V max)
- EN falling threshold (V_EN_L): 0.8V typical
- EN hysteresis: 200mV typical
- EN input current: < 1uA (very high impedance)

For resistor-divider enable (from higher voltage rail PG):
V_EN = V_PG * R_bottom / (R_top + R_bottom)

Design for V_EN > V_EN_H(max) with margin:
V_EN >= V_EN_H(max) * 1.2 = 1.15V * 1.2 = 1.38V minimum

If PG signal is 3.3V (pulled up to 3.3V rail):
Divider ratio: 1.38/3.3 = 0.418 minimum
Choose: R_top = 56k, R_bottom = 47k
V_EN = 3.3 * 47/(56+47) = 1.506V (37% margin over worst-case threshold)

Timing Margin Calculation

Margin between PG assertion and EN threshold crossing:

If using RC delay on EN pin:
t_delay = -R*C * ln(1 - V_threshold/V_final)

Example: R = 100k, C = 100nF, V_final = 3.3V, V_threshold = 1.15V:
t_delay = -100e3*100e-9 * ln(1 - 1.15/3.3)
t_delay = -10ms * ln(0.652) = -10ms * (-0.427) = 4.27ms

Total startup delay for this stage: 4.27ms + soft-start time
Timing margin: Ensure this delay is sufficient for previous rail to be fully stable.

Document EN threshold specifications (min/max) for every regulator in the design.
Calculate actual EN voltage from the driving source (PG signal, divider, supervisor output).
Verify EN voltage exceeds V_EN_H(max) by at least 20% margin.
If RC delay is used, calculate delay time and verify it provides adequate margin.
Check EN disable path: ensure EN can be pulled below V_EN_L(min) reliably for shutdown.
Verify EN does not float during power transitions (add weak pull-down if source can tri-state).

Robust enable chain with proper margins:
Rail 1 PG (3.3V open-drain, 10k pull-up) -> RC delay -> Rail 2 EN
- R_delay = 47k, C_delay = 100nF (gives 3.7ms delay to 1.38V threshold)
- V_EN at steady state: 3.3V * 47k/(47k+0) = 3.3V (direct connection after RC)
- Actually: PG to EN direct with 100nF cap for noise filtering, no series R
- V_EN = 3.3V (2.87x above 1.15V max threshold -- excellent margin)
- Discharge: 100k pull-down on EN ensures disable within 500us of PG deassert

Marginal enable threshold leading to intermittent startup:
PG output from 1.0V rail drives EN directly. PG pulls up to 1.0V rail.
V_EN when asserted = 1.0V.
EN threshold spec: 0.9V min to 1.15V max.
At 1.0V: This is below the 1.15V maximum threshold!
Result: Works on some boards (threshold on low side), fails on others (threshold on high side).
10% of production boards fail to start Rail 2 because V_EN is in the undefined zone.

Checkpoint 6: Discharge Path for Power-Down Critical

When power is removed or a rail is disabled, the output capacitors hold charge that slowly bleeds through leakage. Without an active discharge path, voltage rails can remain elevated for seconds after shutdown, violating power-down sequencing requirements and preventing quick restart. Active discharge circuits ensure controlled power-down.

Discharge Time Without Active Discharge

Natural discharge time through load leakage:
t_discharge = C_out * V_out / I_leakage

Example: 100uF output cap, 3.3V, IC sleep current = 10uA:
t_discharge = 100e-6 * 3.3 / 10e-6 = 33 seconds!

With feedback divider (100k + 56k) as only bleed path:
I_bleed = V_out / (R_top + R_bottom) = 3.3 / 156k = 21uA
t_discharge = 100e-6 * 3.3 / 21e-6 = 15.7 seconds (still too slow!)

Required discharge time for quick restart: typically < 100ms
Required discharge resistor: R = t_discharge / (C * 5) (for 99% discharge)
R = 0.1 / (100e-6 * 5) = 200 ohms
Power dissipation during normal operation: P = V^2/R = 3.3^2/200 = 54mW (wasteful!)

Active Discharge Methods

Method	Mechanism	Pros/Cons
Internal active discharge (built into regulator)	NFET turns on when EN goes low	Simple, no external parts. Fixed discharge rate.
External MOSFET discharge	NFET + resistor activated by inverse of EN	Adjustable rate, higher current capability.
Sequencer-controlled discharge	UCD9090 GPIO drives discharge FET	Programmable, coordinated with sequence.

Sequencer IC Examples

UCD9090 (TI 10-rail sequencer):
- 10 enable/monitor channels
- Programmable power-up and power-DOWN sequence
- Configurable discharge control on each channel
- Fault response: immediate shutdown or graceful sequence-down
- PMBus interface for runtime configuration

TPS65263 (TI triple buck with integrated sequencing):
- 3 synchronous bucks with internal sequencing
- Active output discharge on all channels
- Programmable startup/shutdown order
- Built-in PG with deglitch filter

LTC2924 (Analog Devices 4-channel sequencer):
- Monitors/controls 4 supplies
- Adjustable enable delays via external RC
- Power-down sequencing (reverse order)

Controlled power-down with UCD9090:
Power-down sequence (reverse of power-up):
1. Assert reset to FPGA (hold for 10ms)
2. Disable VCC_IO (3.3V) -- active discharge to 0V in 5ms
3. Wait 2ms
4. Disable VCC_AUX (1.8V) -- active discharge in 3ms
5. Wait 2ms
6. Disable VCC_INT (1.0V) -- active discharge in 2ms
Total power-down: 24ms (fast enough for 50ms power-cycle requirement)

No discharge path causing startup failure:
User quickly power-cycles the board (off for 200ms, then on again).
VCC_IO (3.3V, 200uF output) is still at 2.8V when power returns.
VCC_INT (1.0V) starts fresh from 0V.
Result: VCC_IO > VCC_INT for 3ms -- violates sequencing requirement!
FPGA enters undefined state and fails to configure.
Customer complaint: "Board only works on cold start, not hot restart."

TI Fusion Digital Power Designer: GUI tool for configuring UCD9090/UCD90120 sequencers. Drag-and-drop sequence design with timing visualization.

Power-down simulation: In LTspice, simulate shutdown by switching EN signals and modeling discharge paths. Verify all rails reach 0V within spec time.