Checkpoint 1: Trace Width per IPC-2152 Critical
IPC-2152 (2009) replaced the older IPC-2221 charts for determining current-carrying capacity of PCB traces. The newer standard accounts for board thickness, copper weight, ambient temperature, and whether the trace is internal or external. Under-sized traces cause localized heating, reliability degradation, and in extreme cases, trace fusing (open circuit).
IPC-2152 Calculation Method
The IPC-2152 method uses empirical curves, but the simplified formula is:
I = k * dT^b * A^c
For EXTERNAL traces (IPC-2152 validated):
k = 0.048, b = 0.44, c = 0.725
For INTERNAL traces (IPC-2152):
k = 0.024, b = 0.44, c = 0.725
Where:
I = current (Amperes)
dT = temperature rise above ambient (degrees C)
A = cross-sectional area (mil^2) = width(mil) * thickness(mil)
Solving for width:
A = (I / (k * dT^b))^(1/c)
Width(mil) = A / thickness(mil)
Width(mm) = Width(mil) * 0.0254
Detailed Calculation Examples
Example 1: 3A trace, internal, 1oz copper, 10C rise:
A = (3 / (0.024 * 10^0.44))^(1/0.725)
A = (3 / (0.024 * 2.754))^1.379
A = (3 / 0.0661)^1.379
A = (45.38)^1.379 = 163.7 mil^2
Width = 163.7 / 1.4 = 116.9 mil = 2.97mm
Example 2: 5A trace, external, 2oz copper, 20C rise:
A = (5 / (0.048 * 20^0.44))^(1/0.725)
A = (5 / (0.048 * 3.546))^1.379
A = (5 / 0.1702)^1.379
A = (29.38)^1.379 = 94.5 mil^2
Width = 94.5 / 2.8 = 33.8 mil = 0.86mm
Example 3: 10A trace, internal, 1oz copper, 20C rise:
A = (10 / (0.024 * 20^0.44))^(1/0.725)
A = (10 / 0.0851)^1.379
A = (117.5)^1.379 = 617.3 mil^2
Width = 617.3 / 1.4 = 440.9 mil = 11.2mm
Quick Reference Table (20C Rise, Internal Layer)
| Current (A) |
0.5oz (17um) |
1oz (35um) |
2oz (70um) |
3oz (105um) |
| 1A |
1.0mm |
0.5mm |
0.25mm |
0.18mm |
| 3A |
5.9mm |
3.0mm |
1.5mm |
1.0mm |
| 5A |
14mm |
6.8mm |
3.4mm |
2.3mm |
| 10A |
44mm |
11.2mm |
5.6mm |
3.8mm |
| 20A |
Use plane |
28mm |
14mm |
9.3mm |
Step-by-Step Verification Process
- Identify all power traces in the design (from VRM to load IC, inductor connections, etc.).
- Determine maximum continuous current for each trace (include derating for peaks).
- Identify trace layer (internal vs external) and copper weight.
- Determine maximum allowable temperature rise (consider ambient + self-heating budget).
- Calculate minimum trace width using IPC-2152 formula or charts.
- Verify actual trace width in layout exceeds calculated minimum by at least 20% margin.
- Check for any bottleneck points (component pad transitions, via breakouts, tight routing areas).
Proper power trace sizing (5A buck inductor output):
Trace: SW node to inductor, carries 5A peak (3A average + 2A ripple peak)
Layer: External (top), 2oz copper
Ambient: 55C maximum, board max: 100C (45C rise budget)
Required area = (5/(0.048*45^0.44))^1.379 = (5/0.218)^1.379 = 47.8 mil^2
Width = 47.8/2.8 = 17.1 mil = 0.43mm minimum
Actual design: 2.0mm trace (4.6x margin) -- very conservative and correct.
Temperature rise at 5A: < 3C (negligible)
Under-sized trace causes field failure:
12V input power trace: 3A continuous, routed on internal layer, 0.5oz copper.
Trace width: 0.3mm (12 mil) -- designer used default signal trace width!
Required per IPC-2152 for 20C rise: A = (3/0.0661)^1.379 = 163.7 mil^2
Required width: 163.7/0.7 = 233 mil = 5.9mm needed!
Actual: 0.3mm = 51x undersized!
Result: Trace reaches 170C, board chars and eventually fails open in the field.
- Using IPC-2221 instead of IPC-2152: The old IPC-2221 charts significantly overestimate capacity at lower temperature rises. IPC-2152 is more conservative and accurate.
- Not accounting for ambient temperature: A 20C rise budget at 25C ambient is fine (45C trace). At 70C ambient: 90C trace temperature (approaching limit!).
- Ignoring plating thickness: The copper thickness includes only the base foil. Plating (typically 0.5-1mil) adds negligibly and should not be counted for derating.
- Forgetting via-pad transitions: Where a trace connects to a component pad or via pad, the effective width may narrow. Verify the pad connection width.
Checkpoint 2: Via Current Rating per IPC Critical
Vias carry current between layers and have limited current capacity based on their plating thickness (typically 0.7-1.0 mil/18-25um), barrel diameter, and length. A single standard via (0.3mm drill) carries approximately 0.5-1.5A depending on acceptable temperature rise. Multiple vias must be used in parallel for higher currents.
Via Current Capacity Calculation
Via cross-sectional area (copper barrel):
A_via = pi * ((D_drill/2 + t_plating)^2 - (D_drill/2)^2)
A_via = pi * t_plating * (D_drill + t_plating)
Simplified (for thin plating where t << D):
A_via = pi * D_drill * t_plating
Example: D_drill = 0.3mm (12mil), t_plating = 25um (1mil):
A_via = pi * 0.3 * 0.025 = 0.0236 mm^2 = 0.0236 * 1550 = 36.5 mil^2
Using IPC-2152 formula (treating via as internal conductor):
I_via = 0.024 * dT^0.44 * A^0.725
I_via (10C rise) = 0.024 * 10^0.44 * 36.5^0.725 = 0.024 * 2.75 * 16.8 = 1.11A
I_via (20C rise) = 0.024 * 20^0.44 * 36.5^0.725 = 0.024 * 3.55 * 16.8 = 1.43A
Via Current Rating Table
| Drill Diameter |
Plating (25um) |
Area (mil^2) |
I @ 10C rise |
I @ 20C rise |
| 0.2mm (8mil) |
25um (1mil) |
24.4 |
0.82A |
1.06A |
| 0.3mm (12mil) |
25um (1mil) |
36.5 |
1.11A |
1.43A |
| 0.4mm (16mil) |
25um (1mil) |
48.7 |
1.38A |
1.78A |
| 0.5mm (20mil) |
25um (1mil) |
60.9 |
1.64A |
2.11A |
| 0.8mm (31mil) |
25um (1mil) |
97.4 |
2.34A |
3.02A |
Multiple Vias for High Current
Number of vias needed:
N_vias = I_total / I_per_via (with 20-30% derating for current sharing imbalance)
Example: 10A power connection through vias, 0.3mm drill:
I_per_via = 1.43A (at 20C rise)
N_vias = 10A / (1.43A * 0.8) = 8.7 --> use 9 vias minimum
Conservative: use 12 vias (25% margin over calculated minimum)
Via resistance (for IR drop calculation):
R_via = (rho * L) / A_via
rho (copper) = 1.72e-8 ohm-m
L = board thickness = 1.6mm = 1.6e-3 m
A_via = pi * 0.3e-3 * 25e-6 = 2.36e-8 m^2
R_via = 1.72e-8 * 1.6e-3 / 2.36e-8 = 1.17 mOhm per via
12 vias in parallel: R_total = 1.17/12 = 0.097 mOhm
IR drop: V = 10A * 0.097mOhm = 0.97mV (negligible)
Adequate via array for 15A power transition:
Current: 15A from top-layer regulator output to internal power plane
Via: 0.4mm drill, 25um plating, I_rating = 1.78A per via at 20C rise
N_vias = 15 / (1.78 * 0.75) = 11.2 --> use 12 vias
Layout: 3x4 via array on 1.0mm pitch, connected by 5mm wide copper pour
Thermal simulation confirms: max via temperature = ambient + 14C (within budget)
Single via for 5A power connection:
Designer connects 5A power trace to internal plane with one 0.3mm via.
Via rating: 1.43A at 20C rise. Carrying 5A = 3.5x overloaded!
Via temperature rise: approximately 20C * (5/1.43)^(1/0.44) = 20C * 3.5^2.27 = 330C!
(This would vaporize the via -- calculation shows the severity of overload)
Actual failure mode: Via barrel cracks from thermal stress, intermittent open circuit.
- Assuming via is filled with copper: Standard PTH vias are hollow cylinders. Only the barrel plating carries current, not the full drill diameter.
- Not verifying plating thickness: Specify minimum 25um plating in fab notes. Some budget fabs deliver 18-20um, reducing current capacity by 25%.
- Via filled with solder: If vias are plugged with solder (HASL process), the solder provides additional current path but has 10x higher resistivity than copper.
- Uneven current sharing: Vias closer to the current source carry more current. Array layout and connecting trace geometry affect distribution.
Checkpoint 3: Plane Current Density < 30 A/mm2 Major
While planes are generally wide enough for average current, localized current crowding can exceed safe limits. Critical areas include: near via clusters (BGA breakouts), at plane neck-down points (near board cutouts), and where current enters/exits through limited via connections.
Current Density Analysis
Current density in a plane section:
J = I / (W * t)
Where:
J = current density (A/mm^2)
I = current through the section (A)
W = width of the plane section (mm)
t = copper thickness (mm)
Recommended limits:
J < 15 A/mm^2 for long-term reliability (automotive, aerospace)
J < 30 A/mm^2 for consumer electronics
J < 50 A/mm^2 absolute maximum for short-duration peaks
Temperature rise estimate from current density:
dT = (J / k_thermal)^(1/0.44) [rough approximation]
Example: J = 30 A/mm^2, 1oz copper (0.035mm):
I per mm width = 30 * 0.035 = 1.05 A/mm
This corresponds to approximately 25-35C rise (acceptable for consumer)
Identifying Current Density Hot Spots
- Run DC IR-drop simulation with all loads at maximum current.
- View current density map (color coded: blue=low, red=high).
- Identify all areas exceeding 30 A/mm2 (or your design limit).
- Common hot spots: plane necks near mounting holes, narrow corridors between cutouts, via entry points.
- Widen narrow sections, add copper fills, or redistribute current path to reduce crowding.
- Re-simulate after changes to verify improvement.
Uniform current density verified by simulation:
20A VCCINT plane on 1oz internal layer, board 100x80mm.
DC IR drop simulation shows:
- Maximum current density: 22 A/mm^2 (at via cluster near FPGA)
- Average current density: 8 A/mm^2
- No hot spot exceeds 30 A/mm^2 limit
- Temperature rise at hottest point: 18C (safe margin to 40C budget)
- IR drop from VRM to farthest IC pin: 6mV (0.7% of 0.85V)
Severe crowding at board cutout:
A USB connector cutout creates a 4mm wide neck in the GND plane.
Total ground return current through this section: 8A.
J = 8 / (4 * 0.035) = 57 A/mm^2 (nearly 2x limit!)
Temperature rise: ~60C above ambient.
At 70C ambient: copper at 130C (exceeds FR4 Tg of 130-140C).
Long-term: delamination and eventual open circuit at this location.
Sigrity PowerDC: DC Analysis > Current Density Map. Set threshold coloring at 30 A/mm^2. Red regions indicate violations.
Ansys SIwave: DCIR Analysis > Results > Current Density. Export hotspot coordinates for layout correction.
Cadence Allegro: Thermal analysis add-on shows per-layer current density with color mapping.
Checkpoint 4: Thermal Relief Design Adequate Major
Thermal reliefs (spoke connections) on pads connected to power/ground planes allow soldering by reducing heat sink effect. However, for high-current connections, thermal reliefs add resistance and must be sized appropriately. For power delivery paths carrying > 1A, direct connections (no thermal relief) or wide-spoke reliefs should be used.
Thermal Relief Resistance
Standard thermal relief: 4 spokes, each 0.25mm (10mil) wide, 0.25mm (10mil) long
Resistance per spoke:
R_spoke = rho * L / (W * t)
R_spoke = 1.72e-8 * 0.25e-3 / (0.25e-3 * 35e-6) = 0.49 mOhm
4 spokes in parallel: R_thermal_relief = 0.49/4 = 0.12 mOhm
For 10A through this connection:
V_drop = 10 * 0.12e-3 = 1.2mV (negligible for most applications)
Power dissipation: P = I^2 * R = 100 * 0.12e-3 = 12mW (negligible)
BUT: If spokes are very narrow (5mil) and long (15mil):
R_spoke = 1.72e-8 * 0.38e-3 / (0.13e-3 * 35e-6) = 1.44 mOhm
4 spokes: R = 0.36 mOhm, V_drop at 10A = 3.6mV
With 20 such connections in series: 72mV total drop (8.5% of 0.85V rail!!)
When to Use Different Connection Types
| Connection Type |
Current Rating |
Use Case |
Solderability |
| Direct connect (no relief) |
Unlimited |
Power components, inner vias |
Poor (needs preheat) |
| Wide thermal relief (4x 0.4mm spokes) |
> 5A |
Power pins needing hand rework |
Good |
| Standard thermal relief (4x 0.25mm) |
1-5A |
Signal component power pins |
Very good |
| Narrow thermal relief (2x 0.15mm) |
< 1A |
Test points, low-current signals |
Excellent |
Direct connect for FPGA power vias:
All FPGA VCCINT/GND via connections to internal planes use direct connect (no thermal relief).
Reason: These are never hand-soldered (internal vias), and carry high current.
Result: Zero additional resistance from plane connections.
SMD pads on external layers use wide 4-spoke relief for reflow soldering compatibility.
Narrow thermal reliefs on power connector pads:
12V input connector pad connected to power plane with 2-spoke, 8mil-wide thermal relief.
Current: 5A per pin (2 pins = 10A total)
R_relief per pin = 1.72e-8 * 0.3e-3 / (0.2e-3 * 35e-6) / 2 = 0.37 mOhm per pin
Seems small, but concentrated heating at narrow spokes:
Local temperature at spokes: 45C above ambient (visible as darkened FR4 around the pad).
After 2 years in service: FR4 degradation, increased resistance, eventual intermittent failure.
Checkpoint 5: Fuse Coordination Major
Fuses and other overcurrent protection devices must be coordinated with the trace/via current ratings and downstream load requirements. The fuse must blow before any PCB trace reaches its fusing current, but must not nuisance-trip during normal operation including startup inrush.
Fuse Selection Criteria
Fuse rating selection:
I_fuse_rating >= I_max_continuous * 1.25 (derating for ambient temp)
I_fuse_rating <= I_trace_max * 0.8 (must blow before trace damage)
I^2*t coordination:
Fuse must clear before trace reaches fusing point:
I^2*t_fuse_clear < I^2*t_trace_fuse
Trace fusing current (Onderdonk's equation for short pulses):
I_fuse = A * sqrt((1/t) * ln((T_melt - T_ambient)/(234 + T_ambient) + 1) * 12277)
For 1oz copper trace, 1mm wide (A = 1.4 mil^2 = 0.9e-3 mm^2):
Not applicable directly -- Onderdonk is for wire. Use IPC fusing data instead.
Practical approach:
- Fuse rating: 1.25x to 2x normal operating current
- Fuse I^2*t: Less than trace I^2*t at fusing temperature
- Inrush: Verify fuse survives inrush pulse (slow-blow if needed)
Fuse Types and Applications
| Fuse Type |
Response |
Application |
Example Part |
| Fast-acting (F) |
< 5ms at 10x rating |
Semiconductor protection |
Littelfuse 0467003 |
| Slow-blow (T) |
> 10ms at 10x rating |
Power supply input (inrush tolerant) |
Littelfuse 0454003 |
| PTC Resettable |
Self-resetting |
USB ports, hot-swap |
Bourns MF-MSMF050 |
Coordinated protection for 5V/3A supply:
Input fuse: 5A slow-blow (Littelfuse 0454005, 1206 SMD)
- Normal operating current: 3A (60% of fuse rating -- adequate derating)
- Inrush: 8A for 5ms (within slow-blow fuse tolerance at 1.6x rating)
- Fuse blows at 10A sustained (2x overload) in < 10 seconds
- Downstream trace: 5mm wide, 1oz external (rated for 7A at 20C rise)
- Fuse protects trace: 5A fuse blows before 7A trace limit is reached
Fuse larger than trace capacity:
Input fuse: 10A (chosen for "margin")
Downstream trace: 2mm wide, 1oz internal (rated for 3.5A at 20C rise)
Normal load: 2.5A
Under fault: Current could reach 6A before fuse starts to blow.
At 6A: Trace temperature rise = 20C * (6/3.5)^2.27 = 72C!
Trace chars and fails before fuse clears the fault. Fuse provided NO protection.
Checkpoint 6: Power Connector Current Rating Critical
Power connectors must be rated for the maximum continuous current plus derating for temperature, contact resistance aging, and number of mating cycles. The PCB pad and trace connections to the connector must also be sized appropriately. Connector failures are among the most common power delivery issues in the field.
Connector Derating Guidelines
Manufacturer current rating is typically at 30C rise, 25C ambient, single pin:
Derating factors:
- Temperature: Reduce by 1-2% per degree C above 25C ambient
- Adjacent loaded pins: Reduce by 20-30% if all adjacent pins carry current
- Aging (mating cycles): Reduce by 10-20% after 500+ cycles
- Altitude: Reduce by 5-10% above 3000m (less air cooling)
Effective rating = Rated * k_temp * k_adjacent * k_aging * k_altitude
Example: Molex Mini-Fit Jr, rated 9A per pin at 25C:
At 55C ambient: k_temp = 1 - (55-25)*0.015 = 0.55 --> 9A * 0.55 = 4.95A
With both adjacent pins loaded: k_adjacent = 0.75 --> 4.95 * 0.75 = 3.71A
After 1000 cycles: k_aging = 0.85 --> 3.71 * 0.85 = 3.15A
A "9A connector" may only safely carry 3.15A in real conditions!
Common Power Connectors and Ratings
| Connector |
Per-Pin Rating |
Derated (55C) |
Typical Use |
| Molex Mini-Fit Jr (5557) |
9A |
5A |
Board power input, ATX |
| TE Connectivity MATE-N-LOK |
15A |
9A |
High-power distribution |
| JST XH series |
3A |
2A |
Low-power peripherals |
| Würth WR-TBL terminal block |
20A |
13A |
Industrial power, motor drives |
| USB Type-C |
3A (default) / 5A (PD) |
2.5A / 4A |
Device power, charging |
- Determine maximum continuous current requirement at the connector.
- Select connector with per-pin rating at least 2x the per-pin current need.
- Apply derating factors for your operating environment.
- If single pin insufficient, gang multiple pins for power (common in ATX connectors).
- Verify PCB pad and trace to connector meet IPC-2152 for the full current.
- Specify connector mating force and retention in mechanical design to prevent intermittent contact.
Properly rated connector for 12V/8A board supply:
Requirement: 8A continuous at up to 55C ambient.
Selected: Molex Mini-Fit Jr 4-pin (2 power + 2 ground).
Per pin: 9A rated, derated to 5A at 55C.
2 power pins: 5A * 2 = 10A capacity (25% margin over 8A need).
PCB pads: 3mm wide traces to 2oz copper plane via 4 vias per pad.
Contact resistance: 10 mOhm max per pin (specified in datasheet).
Power loss at connector: 8A^2 * 5mOhm (2 pins parallel) = 320mW (acceptable).
Under-rated connector overheating in field:
System draws 6A at 12V, single JST XH pin used for power (rated 3A!).
Overloaded by 2x nominal rating.
After 6 months: contact resistance increases from 10 to 50 mOhm due to heating oxidation.
Power dissipation at contact: 6^2 * 0.05 = 1.8W (!!)
Connector housing melts. Customer returns product with "burning smell" complaint.
