Checkpoint 1: Input Capacitor ESR Within Datasheet Range Critical
Input capacitors for voltage regulators serve two purposes: providing instantaneous current during switching transitions and filtering input voltage ripple. The ESR of input capacitors directly affects input voltage ripple, regulator stability (for LDOs), and EMI performance. Too high ESR causes excessive ripple; too low ESR can cause ringing.
Input Capacitor Requirements for Buck Converters
Input RMS current for buck converter:
I_rms_in = I_out * sqrt(D * (1-D))
Where D = V_out/V_in (duty cycle)
Maximum RMS occurs at D = 0.5:
I_rms_max = I_out * 0.5
Input voltage ripple:
V_ripple_in = I_out * D * (1-D) / (f_sw * C_in) + I_rms * ESR
Example: TPS54331 (5V to 1.8V, 3A, f_sw = 570kHz):
D = 1.8/5 = 0.36
I_rms = 3 * sqrt(0.36 * 0.64) = 1.44A
V_ripple = 3*0.36*0.64/(570e3*22e-6) + 1.44*5e-3
V_ripple = 55mV + 7.2mV = 62.2mV
TPS54331 datasheet recommends: 10uF minimum, X5R/X7R ceramic
Selected: 2x 10uF 0805 X7R (GRM21BR71A106KE51) = 20uF effective
Design Example: TPS62130 (3.3V to 1.8V, 3A)
TPS62130 input requirements (from datasheet):
- Minimum input capacitance: 10uF ceramic
- Recommended: 2x 10uF X5R/X7R, voltage rating >= 1.5x V_in
- ESR: Must be < 10 mOhm (ceramic MLCC meets this easily)
Selected: 2x Murata GRM21BR61A106ME19 (10uF, 10V, X5R, 0805)
- ESR at 570kHz: 3 mOhm (from Murata SimSurfing)
- Effective capacitance at 3.3V DC bias: ~6.5uF each (13uF total)
- Voltage rating: 10V (3x operating - adequate derating)
- I_rms rating: 3A each (exceeds 1.44A requirement)
Input Capacitor for LDOs (ESR-Sensitive)
LM1117-3.3 LDO input requirements:
- Minimum: 10uF
- ESR range for stability: NOT specified for input (flexible)
- However: Output cap ESR is CRITICAL (see Checkpoint 2)
For LDOs, input cap ESR affects:
1. High-frequency input noise rejection
2. Prevention of input LC resonance with source inductance
3. Suppression of LDO input current spikes
Recommendation: Use ceramic MLCC (low ESR) plus small series
ferrite bead if input trace is long (prevents LC oscillation).
- Check regulator datasheet for input capacitor requirements (value, ESR range, type).
- Select capacitor voltage rating >= 1.5x maximum input voltage (derating for MLCC DC bias).
- Verify effective capacitance at operating DC bias using manufacturer tools (SimSurfing, SEAT).
- Calculate RMS ripple current and verify capacitor current rating is adequate.
- Place input cap within 5mm of regulator VIN pin with short, wide traces.
- For high-current bucks (>5A): use multiple input caps in parallel to share RMS current.
TPS54331 input capacitor design (12V to 3.3V, 3A):
D = 3.3/12 = 0.275, I_rms = 3*sqrt(0.275*0.725) = 1.34A
Selected: 2x 10uF 25V X7R 0805 (Murata GRM21BR71E106KA73)
- Effective C at 12V bias: 5.5uF each, 11uF total
- ESR: 4 mOhm each, 2 mOhm parallel
- Ripple current rating: 2.5A each (1.34A shared = 0.67A each - OK)
- Placed within 3mm of VIN pin, ground vias adjacent
- Input ripple: 40mV p-p (well within 12V +/-5% spec)
Electrolytic input cap causing ringing:
Designer uses 100uF/25V aluminum electrolytic with ESR = 200 mOhm.
Input trace from connector: 10cm long, 0.5mm wide = ~50nH inductance.
LC resonance: f = 1/(2*pi*sqrt(50e-9*100e-6)) = 71kHz
Q factor: Q = 1/(ESR * sqrt(C/L)) = 1/(0.2*sqrt(100e-6/50e-9)) = 0.11
Actually over-damped here, but with MLCC (ESR=3mOhm):
Q = 1/(0.003*sqrt(100e-6/50e-9)) = 7.5 -- significant ringing!
Solution: Add series ferrite (BLM18PG121SN1D) or use 1-ohm series R with small cap.
- Not derating MLCC for DC bias: A 10uF X5R cap at its rated voltage may only provide 3-4uF. Always check bias curves.
- Single input cap for high-di/dt load: One cap may not handle the RMS current. Use 2-3 in parallel for thermal distribution.
- Placing input cap far from VIN pin: Even 5mm of trace adds significant inductance at switching frequencies, increasing ringing.
- Ignoring input filter interaction: If an LC filter precedes the regulator, its resonance can interact with the regulator's input impedance.
Checkpoint 2: Output Capacitor ESR/ESL Meets Stability Requirements Critical
The output capacitor is the most critical component for regulator stability. For LDOs, the ESR directly affects the control loop phase margin. For buck converters, the output capacitor determines ripple voltage, transient response, and loop compensation requirements.
LDO Output Capacitor ESR (LM1117 Example)
LM1117 stability requirements (from datasheet):
- Output capacitance: 10uF minimum
- Output ESR range: 0.3 ohm to 22 ohm (CRITICAL for stability!)
- Without proper ESR, LM1117 WILL oscillate
Why ESR matters for LDO stability:
The ESR zero (f_z = 1/(2*pi*ESR*C_out)) provides phase boost:
- Too low ESR: zero moves too high in frequency, insufficient phase margin
- Too high ESR: excessive output ripple, poor transient response
Example with 10uF output:
f_z (ESR=0.3ohm) = 1/(2*pi*0.3*10e-6) = 53 kHz (provides phase boost at crossover)
f_z (ESR=22ohm) = 1/(2*pi*22*10e-6) = 723 Hz (too low, not useful)
f_z (ESR=0.01ohm/ceramic) = 1/(2*pi*0.01*10e-6) = 1.59 MHz (too high!)
IMPORTANT: Standard MLCC (ESR < 10 mOhm) will NOT stabilize LM1117!
Solution: Use tantalum/polymer cap, or add series resistance to MLCC.
Buck Converter Output Capacitor (TPS62130 Example)
TPS62130 output ripple calculation:
Inductor ripple current:
dI_L = (V_in - V_out) * D / (f_sw * L)
dI_L = (3.3 - 1.8) * 0.545 / (2.5e6 * 2.2e-6) = 0.149A
Output voltage ripple (ESR-dominated for polymer caps):
V_ripple = dI_L * ESR_out + dI_L / (8 * f_sw * C_out)
With 22uF ceramic (ESR = 3mOhm):
V_ripple = 0.149 * 0.003 + 0.149/(8*2.5e6*22e-6)
V_ripple = 0.45mV + 0.34mV = 0.79mV (excellent!)
With 47uF polymer (ESR = 25mOhm):
V_ripple = 0.149 * 0.025 + 0.149/(8*2.5e6*47e-6)
V_ripple = 3.7mV + 0.16mV = 3.9mV (still good)
Output Cap Selection for Common Regulators
| Regulator |
Type |
C_out Minimum |
ESR Requirement |
Recommended Part |
| LM1117 |
LDO |
10uF |
0.3-22 ohm |
Kemet T491A106K010AT (10uF tantalum) |
| TPS7A4901 |
LDO |
10uF |
Any (stable with ceramic) |
GRM21BR61A106ME19 (10uF MLCC) |
| TPS62130 |
Buck |
22uF |
< 20 mOhm |
GRM21BR60J226ME39 (22uF MLCC) |
| TPS54331 |
Buck |
47-100uF |
< 30 mOhm |
2x GRM31CR60J476ME19 (47uF MLCC) |
Ceramic-stable LDO with proper output cap:
TPS7A4901 (3.3V, 150mA) for sensitive analog supply:
- Output: 2x 10uF 0805 X7R ceramic (GRM21BR61A106ME19)
- ESR at DC: 3 mOhm each, 1.5 mOhm parallel
- Stable with any ESR (designed for ceramic output)
- Output noise: 15.4 uVrms (excellent for ADC reference supply)
- Additional 100nF close to load IC for HF filtering
LM1117 with ceramic output cap (oscillation):
Designer replaced tantalum with 10uF X5R ceramic (ESR = 3 mOhm).
ESR zero: f_z = 1/(2*pi*0.003*10e-6) = 5.3 MHz (way above loop bandwidth)
Result: No phase boost at crossover. Phase margin drops to -5 degrees.
LDO oscillates at 150 kHz with 200mV output ripple!
Fix: Add 0.5 ohm resistor in series with ceramic, or replace with polymer tantalum.
- Assuming all LDOs work with ceramic: Older LDO designs (LM1117, LM317, LT1117) REQUIRE ESR for stability. Only newer "ceramic-stable" LDOs work with MLCC.
- Not checking ESR at operating temperature: Tantalum ESR increases at cold temperatures. A 0.5 ohm room-temp ESR may be 2 ohm at -40C.
- Output cap placed too far from VOUT pin: Trace inductance between regulator and output cap adds to ESL, degrading transient response.
Checkpoint 3: Feedback Resistor Divider Accurate (+-1%) Major
Adjustable voltage regulators use a resistor divider to set the output voltage. The resistor tolerance directly affects output voltage accuracy. For tight-tolerance supplies (DDR termination, processor core), 0.1% resistors may be required.
Feedback Divider Calculation
Standard feedback equation (most regulators):
V_out = V_ref * (1 + R_top/R_bottom)
Or equivalently:
R_top/R_bottom = (V_out/V_ref) - 1
Where:
V_ref = internal reference voltage (e.g., 0.8V for TPS62130)
R_top = resistor from VOUT to FB pin
R_bottom = resistor from FB pin to GND
Example: TPS62130, V_out = 1.8V, V_ref = 0.8V
R_top/R_bottom = (1.8/0.8) - 1 = 1.25
Choose R_bottom = 100k (datasheet recommended range: 10k-200k)
R_top = 1.25 * 100k = 125k (use 124k standard 1% value)
Actual V_out = 0.8 * (1 + 124k/100k) = 0.8 * 2.24 = 1.792V
Error = (1.792 - 1.8)/1.8 = -0.44% (acceptable)
Tolerance Analysis
Worst-case output voltage with 1% resistors:
V_out_max = V_ref * (1 + R_top_max/R_bottom_min)
V_out_max = 0.8 * (1 + 124k*1.01 / 100k*0.99)
V_out_max = 0.8 * (1 + 125.24k/99k) = 0.8 * 2.265 = 1.812V (+0.67%)
V_out_min = V_ref * (1 + R_top_min/R_bottom_max)
V_out_min = 0.8 * (1 + 124k*0.99 / 100k*1.01)
V_out_min = 0.8 * (1 + 122.76k/101k) = 0.8 * 2.215 = 1.772V (-1.56%)
Total tolerance band: +0.67% / -1.56%
Including V_ref tolerance (+/-1%): Total = +/-2.6%
For 0.1% resistors: Band reduces to +/-0.3% from divider (much tighter)
Resistor Selection Guidelines
- Start with R_bottom in datasheet-recommended range (typically 10k-200k for low-power, 1k-10k for high-power).
- Calculate R_top for desired output voltage.
- Select nearest standard E96 (1%) or E192 (0.5%) resistor value.
- Verify actual output voltage with selected standard values.
- Calculate worst-case tolerance band including V_ref tolerance.
- If tolerance exceeds load requirement, upgrade to 0.1% resistors or adjust values.
- Add feedforward capacitor across R_top if needed for compensation (see Checkpoint 4).
TPS54331: 12V to 5.0V, 1% accuracy required:
V_ref = 0.8V, V_out = 5.0V
R_top/R_bottom = (5.0/0.8) - 1 = 5.25
R_bottom = 10.0k (1% tolerance)
R_top = 52.5k --> nearest E96 = 52.3k
V_out_actual = 0.8 * (1 + 52.3/10.0) = 4.984V (-0.32%)
With 0.1% resistors: total band = +/-0.52% (meets 1% spec with margin).
Parts: Panasonic ERJ-2RKF1002X (10.0k) + ERJ-2RKF5232X (52.3k)
5% resistors used for DDR4 VTT (0.6V +/-3%):
R_top = 100k (5%), R_bottom = 47k (5%)
Worst case: V_out = 0.8*(1+105k/44.65k) = 2.68V or V_out = 0.8*(1+95k/49.35k) = 2.34V
Wait -- this divider gives 1.5V nominal, not 0.6V. Let me recalculate:
For 0.6V: R_top/R_bottom = (0.6/0.8)-1... V_out < V_ref, need different topology.
Actually for V_out < V_ref: R_bottom divides to FB. Use proper topology per datasheet.
Checkpoint 4: Compensation Network Properly Tuned Critical
The compensation network shapes the control loop frequency response to achieve adequate phase margin (>45 degrees) and gain margin (>10dB) while maximizing bandwidth for fast transient response. Incorrect compensation leads to oscillation, ringing, or sluggish response.
Type II Compensation (Most Common for Voltage-Mode Bucks)
Type II compensator places one zero and one pole plus integrator:
Components: R1 (from output to FB), R2 (FB to COMP), C1 (COMP to GND), C2 (across R2)
Zero frequency: f_z = 1 / (2*pi*R2*C1)
Pole frequency: f_p = 1 / (2*pi*R2*C2)
Mid-band gain: A_mid = R2/R1 * (gm or gain factor)
Design targets:
- Place zero at or below LC double pole: f_z <= f_LC = 1/(2*pi*sqrt(L*C_out))
- Place pole at or above ESR zero: f_p >= f_ESR = 1/(2*pi*ESR*C_out)
- Crossover frequency: f_c = f_sw/10 to f_sw/5 (50-200 kHz typical)
- Phase margin at crossover: > 45 degrees (target 55-65 degrees)
TPS54331 Compensation Example
TPS54331: 12V to 3.3V, 3A, f_sw = 570kHz
L = 10uH, C_out = 2x 47uF ceramic (effective 60uF at bias)
LC double pole: f_LC = 1/(2*pi*sqrt(10e-6*60e-6)) = 6.5 kHz
ESR zero (ceramic): f_ESR = 1/(2*pi*3e-3*60e-6) = 884 kHz
Target crossover: f_c = 570kHz/8 = 71 kHz
Type II compensation (per TPS54331 datasheet method):
R_comp = 15.8k (sets crossover gain)
C_comp = 6.8nF (places zero at f_LC: 1/(2*pi*15.8k*6.8e-9) = 1.5kHz)
C_HF = 33pF (places pole at: 1/(2*pi*15.8k*33e-12) = 305kHz)
Resulting phase margin: 62 degrees (excellent)
Gain margin: 14 dB (good)
Verification Methods
- WEBENCH/Design Tool: Use TI WEBENCH Power Designer to auto-calculate compensation values. Verify Bode plot shows PM > 45deg.
- LTspice Simulation: Build full regulator circuit and run AC analysis. Measure gain and phase at feedback node.
- Bench Measurement: Use network analyzer (e.g., Bode 100) with injection transformer to measure actual loop gain.
- Step Response: Apply 50% load step and observe output. Ringing indicates low phase margin. Slow recovery indicates low bandwidth.
Well-compensated TPS62130 (3.3V to 1.8V, 3A):
TPS62130 uses internal compensation (no external network needed).
Output capacitor: 22uF ceramic (determines loop response).
Measured Bode plot: BW = 180kHz, PM = 58 degrees, GM = 12 dB.
Load step response (0 to 3A in 1us):
- Undershoot: 45mV (within 3% of 1.8V)
- Recovery time: 15us
- No ringing (well-damped)
Under-compensated buck converter (oscillating):
Designer copied compensation from different output voltage/load application note.
- Phase margin: 12 degrees (critically unstable!)
- Output shows 80kHz oscillation with 200mV amplitude
- Gets worse at light load (loop gain increases)
- Audible noise from inductor (magnetostriction at oscillation frequency)
Fix: Reduce R_comp by 3x, increase C_comp by 2x to move crossover lower.
Checkpoint 5: Inductor Saturation Current Adequate Critical
The power inductor in a switching regulator must not saturate at peak current. Saturation causes inductance to drop dramatically (sometimes to 10% of nominal), resulting in extremely high current spikes that can destroy the IC, overheat the inductor, and damage output capacitors.
Peak Inductor Current Calculation
For continuous conduction mode (CCM) buck converter:
I_L_peak = I_out + dI_L/2
Where ripple current:
dI_L = (V_in - V_out) * D / (f_sw * L)
dI_L = (V_in - V_out) * V_out / (V_in * f_sw * L)
Example: TPS54331 (12V to 3.3V, 3A, L=10uH, f_sw=570kHz):
dI_L = (12 - 3.3) * 3.3 / (12 * 570e3 * 10e-6) = 0.42A
I_L_peak = 3.0 + 0.42/2 = 3.21A
Inductor requirement:
I_sat >= I_L_peak * 1.2 (20% margin) = 3.85A
I_sat >= I_OCP (overcurrent protection threshold) for full protection
TPS54331 OCP = 4.3A, so I_sat >= 4.3A
Selected: Wurth 744043100 (10uH, I_sat = 4.8A, DCR = 36 mOhm)
Inductor Selection Criteria
| Parameter |
Requirement |
How to Verify |
| Saturation Current (I_sat) |
>= max(I_peak*1.2, I_OCP) |
Datasheet (at -30% L drop point) |
| RMS Current (I_rms) |
>= I_out (thermal rating) |
Datasheet (at 40C rise) |
| DCR (DC Resistance) |
As low as practical |
P_loss = I_out^2 * DCR |
| Temperature Rating |
>= max ambient + self-heating |
Derate I_sat at temperature |
Proper inductor selection for TPS62130 (3A):
L = 2.2uH (datasheet recommended for 3.3V to 1.8V)
I_peak = 3A + (3.3-1.8)*1.8/(3.3*2.5e6*2.2e-6)/2 = 3A + 0.07A = 3.07A
OCP threshold: 4.5A
Selected: Coilcraft XAL4020-222MEB
- I_sat (30% drop): 7.2A (2.3x margin over peak, exceeds OCP)
- I_rms (40C rise): 5.0A (1.67x margin over I_out)
- DCR: 28 mOhm (power loss: 3^2 * 0.028 = 252mW -- acceptable)
- Size: 4.0mm x 4.0mm x 2.1mm (fits in tight layout)
Undersized inductor saturating at load:
Designer selects cheap inductor: 10uH, I_sat = 3.5A, for 3A output.
I_peak = 3.21A (seems OK, only 92% of rating)
BUT: At 85C ambient, ferrite permeability drops 15% and I_sat drops to 3.0A!
At full load in summer conditions: inductor saturates.
Current spikes to 8A during saturation, triggering OCP hiccup mode.
Output oscillates between 3.3V and 0V at 50kHz (hiccup rate).
Checkpoint 6: Load Transient Response Verified Major
Load transient response measures how well the regulator maintains output voltage during sudden current changes. This is the ultimate test of the complete power supply design (VRM + output caps + compensation + layout). It must be measured in lab to validate simulation.
Transient Response Parameters
Key specifications:
- Undershoot (load step up): V_out drops during sudden current increase
- Overshoot (load step down): V_out rises during sudden current decrease
- Recovery time: Time to settle within regulation band after transient
- Ringing: Number and amplitude of oscillation cycles
First-order undershoot estimate:
V_undershoot = dI * ESL / dt + dI * ESR + dI * t_response / C_out
Example: TPS54331, 3.3V output, 0A to 3A step in 1us:
ESL contribution: 3A * 1nH / 1us = 3mV (negligible)
ESR contribution: 3A * 3mOhm = 9mV
Capacitor charge: 3A * 20us / 94uF = 638mV (dominant during VRM response!)
Worst-case total: ~650mV undershoot without fast VRM
With proper compensation (BW=70kHz, response time ~5us):
Actual undershoot: 3A * 5us / 94uF = 160mV + ESR term = 169mV
This is 5.1% of 3.3V -- borderline, may need more output capacitance.
Measurement Setup
- Use electronic load with fast transient mode (slew rate > 1A/us).
- Set load step from 10% to 90% of rated current (or per application profile).
- Probe output voltage at the IC power pins (not at regulator output) to include PDN effects.
- Use 500MHz+ bandwidth oscilloscope with short ground lead (tip-and-barrel probe or solder-in).
- Capture both load-step-up and load-step-down transients.
- Measure: peak undershoot, peak overshoot, recovery time, ringing frequency.
- Verify all values within specification at room temp, hot, and cold extremes.
TI WEBENCH: Use "Transient Analysis" in Power Designer to simulate load step response before hardware is available.
LTspice: Add .tran analysis with pulsed current source at output. Measure voltage excursion.
Bench Setup: Use Chroma 63600 series or BK Precision 8600 series electronic load. Set transition time to match application di/dt.
Passing transient response:
TPS62130 (1.8V, 3A), step from 0.3A to 2.7A in 500ns:
- Undershoot: 72mV (4.0% of 1.8V) -- within 5% spec
- Overshoot on release: 55mV (3.1%) -- within 5% spec
- Recovery time: 12us to within 1% band
- No ringing (single undershoot/overshoot, well-damped)
- Consistent at -40C to +85C
Failing transient with excessive ringing:
Regulator shows 4 cycles of ringing after load step:
- Peak undershoot: 180mV (10% -- exceeds 5% limit!)
- Ringing frequency: 45kHz (indicates loop phase margin < 30 degrees)
- Recovery time: 85us (specification: 50us max)
Root cause: Compensation optimized for different output capacitor (designer changed 47uF polymer to 22uF ceramic without updating compensation).
