Decoupling Capacitors & Target Impedance — Detailed Tutorial
Comprehensive guide covering what decoupling is, real capacitor models (ESR, ESL, SRF), target impedance calculation, PDN impedance design strategy, capacitor selection & placement, and common mistakes — with animated visualizations.
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Checkpoint 1: Bulk Capacitors (100uF+) Near Regulator Output Critical
Bulk capacitors provide energy storage for low-frequency transient demands (DC to ~500kHz). They are the first line of defense when the VRM cannot respond quickly enough to load changes. These must be placed close to the VRM output to minimize the inductance between the VRM and the bulk capacitor bank.
Bulk Capacitor Requirements
Minimum bulk capacitance for load step:
C_bulk = I_step * t_response / V_droop
Where:
I_step = Load current step (A)
t_response = VRM response time (typically 10-50us for buck converters)
V_droop = Allowable voltage droop during transient
Example: I_step = 10A, t_response = 20us, V_droop = 30mV
C_bulk = 10 * 20e-6 / 30e-3 = 6,667 uF
Practical: Use 8x 1000uF or 15x 470uF polymer capacitors
Recommended Bulk Capacitor Types
| Type |
Part Number |
Value |
ESR |
ESL |
SRF |
| Polymer Aluminum |
Panasonic SVP Series (16SVP470M) |
470uF / 16V |
12 mOhm |
2.5 nH |
147 kHz |
| Polymer Tantalum |
Kemet T520 (T520B477M006ATE025) |
470uF / 6.3V |
25 mOhm |
3 nH |
134 kHz |
| MLCC (High-Cap) |
Murata GRM32ER60J107ME20 |
100uF / 6.3V |
3 mOhm |
1.2 nH |
459 kHz |
Placement Guidelines
- Place bulk capacitors within 10mm of VRM output pins (inductor output node).
- Connect with wide traces or direct plane connection (minimize loop area to ground).
- Use multiple vias (4+ per pad) for ground connection to reduce mounting ESL.
- Distribute bulk caps on both sides of the board near the VRM if space is tight on one side.
- Ensure the current path from bulk cap through plane to IC has minimal impedance (no narrow necks or splits).
Proper bulk cap placement for 20A FPGA rail:
VRM: ISL8225M (20A output), BW = 200kHz, response time = 15us
Required: C = 20A * 15us / 40mV = 7500uF
Implementation: 8x 1000uF Panasonic SVP (16SVP1000M), placed within 8mm of VRM
Parallel ESR: 12mOhm / 8 = 1.5 mOhm
Parallel ESL: 2.5nH / 8 = 0.31 nH
Effective up to: 1/(2*pi*sqrt(0.31nH * 8000uF)) = 100 kHz (overlaps with VRM BW)
Insufficient bulk capacitance:
VRM: 20A output with only 2x 100uF MLCC bulk caps (200uF total)
Load step: 10A in 1us
V_droop = I * t / C = 10 * 15e-6 / 200e-6 = 750mV droop!
On a 1.0V rail, this means voltage drops to 250mV -- device resets immediately.
- Using aluminum electrolytics with high ESR: Standard Al-electrolytic ESR (100-500 mOhm) is often too high. Use polymer types (5-25 mOhm) for digital loads.
- Placing bulk caps far from VRM: Long trace/via path adds inductance, reducing the effective frequency range of bulk caps.
- Not checking voltage derating: Electrolytic capacitors lose capacitance at high temperature. A 470uF cap may be only 350uF at 85C.
- Ignoring inrush current: Large bulk capacitance causes high inrush at power-up. May need soft-start or current limiting.
Checkpoint 2: Mid-Frequency Capacitors (1-10uF) Distributed Critical
Mid-frequency decoupling capacitors (1uF to 10uF MLCC) bridge the gap between bulk capacitors and high-frequency decoupling. They are effective in the 500kHz to 50MHz range and should be distributed across the board near clusters of ICs rather than concentrated in one location.
Frequency Coverage Calculation
10uF 0805 MLCC (e.g., Murata GRM21BR61A106ME19):
C = 10uF (effective at 1.0V DC bias: ~7uF for X5R)
ESR = 3 mOhm
ESL (mounted) = 0.8 nH
f_SRF = 1/(2*pi*sqrt(0.8e-9 * 10e-6)) = 1.78 MHz
Effective range: 200 kHz to 20 MHz
2.2uF 0402 MLCC (e.g., Murata GRM155R60J225ME15):
C = 2.2uF (effective at 3.3V DC bias: ~1.5uF for X5R)
ESR = 5 mOhm
ESL (mounted) = 0.5 nH
f_SRF = 1/(2*pi*sqrt(0.5e-9 * 2.2e-6)) = 4.8 MHz
Effective range: 500 kHz to 50 MHz
Distribution Strategy
- Calculate total mid-frequency capacitance needed: N = Z_target_at_SRF / ESR_single (for parallel impedance to meet target).
- Distribute capacitors evenly within 20mm radius of each major IC.
- Place on power rail side closest to the IC (same layer preferred).
- For multi-IC boards, provide at least 2x 10uF per IC cluster, plus additional as needed.
- Verify that the parallel combination achieves Z < Z_target at the SRF frequency.
Specific Part Recommendations
| Application |
Part Number |
Package |
Qty per IC |
| FPGA VCCINT (0.85V, 20A) |
Murata GRM21BR60J106ME19 (10uF/6.3V) |
0805 |
20-40 |
| DDR4 VDD (1.2V, 4A) |
TDK C1005X5R0J475M (4.7uF/6.3V) |
0402 |
4-8 |
| SoC 1.8V I/O (3A) |
Murata GRM155R60J225ME15 (2.2uF/6.3V) |
0402 |
6-12 |
Distributed mid-frequency decoupling for multi-IC board:
Board has: FPGA + 2x DDR4 + Ethernet PHY + Processor
- FPGA: 30x 10uF 0805 around perimeter, 10x 4.7uF 0402 under BGA
- Each DDR4: 4x 4.7uF 0402 near each chip
- Ethernet PHY: 2x 10uF 0805 + 4x 2.2uF 0402
- Processor: 20x 10uF 0805 + 8x 4.7uF 0402
Total provides flat impedance from 200kHz to 50MHz across entire board.
All mid-caps concentrated near VRM only:
All 20x 10uF caps placed within 5mm of VRM output.
IC is 60mm away from the VRM. At 10MHz:
- Plane inductance from cap cluster to IC: ~2nH
- Additional impedance: 2*pi*10e6*2e-9 = 126 mOhm
- Caps are ineffective at the IC location above 5MHz!
Solution: Distribute caps between VRM and IC, with majority near IC.
Checkpoint 3: High-Frequency Capacitors (100nF) at Every IC Critical
100nF (0.1uF) capacitors are the workhorses of high-frequency decoupling, effective from approximately 5MHz to 200MHz. Every digital IC requires at least one 100nF capacitor per power pin pair, placed as close as physically possible to the pin.
Why 100nF at Every Power Pin
100nF 0402 MLCC (e.g., Murata GRM155R71C104KA88):
C = 100nF
ESR = 10 mOhm (at SRF)
ESL (mounted, via-in-pad) = 0.4 nH
ESL (mounted, trace connection) = 0.8-1.2 nH
f_SRF (via-in-pad) = 1/(2*pi*sqrt(0.4e-9 * 100e-9)) = 25.2 MHz
f_SRF (trace mount) = 1/(2*pi*sqrt(1.0e-9 * 100e-9)) = 15.9 MHz
Effective decoupling range: 2 MHz to 150 MHz (via-in-pad)
Effective decoupling range: 2 MHz to 80 MHz (trace connection)
Impedance at SRF: Z = ESR = 10 mOhm (single cap)
With N caps in parallel: Z = ESR/N = 10/N mOhm
Placement Rules
- One 100nF cap per VDD/GND pin pair minimum. For ICs with many power pins, group caps to cover each pin cluster.
- Maximum distance from cap to IC power pin: 3mm (preferred: <1.5mm).
- Orient capacitor so current loop area is minimized (cap pads aligned with power/ground via pair).
- Use 0402 or 0201 package for minimal body ESL and to fit close to IC.
- For QFP packages: place caps on opposite side directly under power pins.
- For BGA packages: place caps in the escape routing area between via rows.
Part Selection - Murata GRM Series
| Part Number |
Package |
Voltage |
Dielectric |
Tolerance |
| GRM155R71C104KA88 |
0402 |
16V |
X7R |
+/-10% |
| GRM033R71A104KA01 |
0201 |
10V |
X7R |
+/-10% |
| GRM188R71C104KA01 |
0603 |
16V |
X7R |
+/-10% |
Proper HF decoupling on STM32 microcontroller (LQFP-64):
IC has 5 VDD pins and 5 VSS pins.
- 5x 100nF 0402 (GRM155R71C104KA88) placed on bottom layer directly under each VDD/VSS pair
- Each cap within 1mm of its associated power pin via
- Via-in-pad construction eliminates trace routing
- Additional 2x 4.7uF 0402 near pins 1 and 32 for mid-frequency coverage
- 1x 1uF 0402 on VDDA (analog supply) with separate via to analog ground
Single 100nF cap for entire IC:
Xilinx FPGA with 48 VCCINT pins, designer places only 4x 100nF caps on board edge.
- Average distance from cap to power pin: 25mm
- Spreading inductance at 25mm: ~3nH
- At 50MHz: Z_spreading = 2*pi*50e6*3e-9 = 942 mOhm -- completely useless!
- Need 48+ caps placed within 3mm of respective pins.
- Using 0805 when 0402 fits: 0805 package has ~2x the ESL of 0402. Always use smallest practical package for HF decoupling.
- DC bias derating ignored: 100nF X5R at 3.3V may only be 60nF effective. Use X7R or higher voltage rating to maintain capacitance.
- Routing trace between cap pad and via: Even 0.5mm trace adds 0.3-0.5nH. Use via-in-pad to eliminate this.
- Sharing vias between multiple caps: Each cap should have dedicated vias for minimal loop inductance.
Checkpoint 4: Ultra-High-Frequency Capacitors (1-10nF) for GHz ICs Major
For ICs operating at GHz clock rates (high-speed FPGAs, processors, SerDes transceivers), ultra-high-frequency decoupling capacitors (1nF to 10nF) are essential. These operate in the 100MHz to 1GHz+ range where standard 100nF caps have become inductive.
UHF Capacitor Characteristics
1nF 0201 C0G (e.g., Murata GRM0335C1H102JA01):
C = 1nF, ESR = 80 mOhm, ESL = 0.25 nH (via-in-pad)
f_SRF = 1/(2*pi*sqrt(0.25e-9 * 1e-9)) = 318 MHz
Effective range: 50 MHz to 2 GHz
10nF 0402 X7R (e.g., TDK C0402X7R1A103K):
C = 10nF, ESR = 30 mOhm, ESL = 0.4 nH (via-in-pad)
f_SRF = 1/(2*pi*sqrt(0.4e-9 * 10e-9)) = 79.6 MHz
Effective range: 10 MHz to 500 MHz
470pF 0201 C0G (e.g., Murata GRM0335C1H471JA01):
C = 470pF, ESR = 120 mOhm, ESL = 0.2 nH (via-in-pad)
f_SRF = 1/(2*pi*sqrt(0.2e-9 * 470e-12)) = 519 MHz
Effective range: 80 MHz to 3 GHz
When UHF Caps Are Required
- FPGA with transceivers running at 10+ Gbps (clock > 5 GHz)
- High-speed processors (ARM Cortex-A series at 1GHz+)
- DDR4/DDR5 memory interfaces (1.6-4.8 GHz data rate)
- Any IC with rise times below 200ps (f_knee > 1.75 GHz)
- SerDes devices (PCIe Gen3/4/5, USB 3.x, Ethernet 10G+)
- Identify ICs requiring UHF decoupling based on clock/data rates.
- Calculate f_knee = 0.35/t_rise. If f_knee > 200MHz, UHF caps needed.
- Select capacitor values with SRF in the 200MHz-1GHz range.
- Place within 1mm of IC power pins (inside BGA field if possible).
- Use 0201 package exclusively for lowest ESL (0.2-0.3nH mounted).
- Use C0G/NP0 dielectric for stable capacitance (no DC bias or temperature derating).
UHF decoupling for Xilinx UltraScale+ FPGA (GTH 16.3 Gbps transceivers):
VCCINT = 0.85V, f_knee = 0.35/25ps = 14 GHz
- 40x 1nF 0201 C0G placed within BGA field (under IC, bottom layer)
- 20x 470pF 0201 C0G interleaved with 1nF caps
- Via-in-pad construction on all UHF caps
- Plane pair (L2-L3) with 2mil dielectric provides additional 3nF/cm2 plane capacitance
- Combined impedance: < 2 mOhm from 100MHz to 800MHz
No UHF decoupling on 5 GHz processor:
Designer uses only 100nF caps (effective to ~100MHz)
Above 100MHz, impedance rises as 100nF caps become inductive.
At 500MHz: Each 100nF cap presents Z = 2*pi*500e6*0.8e-9 = 2.5 ohms!
Even 60 caps in parallel: Z = 2.5/60 = 42 mOhm (above 5 mOhm target)
Result: High-frequency noise on supply causes jitter in SerDes links.
Murata SimSurfing Tool: Free online tool to get exact S-parameter models for Murata capacitors. Export S2P files for simulation.
URL: https://ds.murata.co.jp/simsurfing/
TDK SEAT Tool: Similar tool for TDK capacitor models. Provides impedance vs frequency with mounting conditions.
In Sigrity: Import manufacturer S2P models directly into component library for accurate simulation.
Checkpoint 5: Capacitor Mounting Inductance Minimized Critical
The mounting inductance (also called loop inductance or parasitic ESL) of a decoupling capacitor often dominates over the body inductance. A perfectly selected capacitor with poor mounting can be 3-5x less effective than its datasheet suggests. Mounting inductance includes: pad-to-via trace, via barrel, and current return path through ground.
Mounting Inductance Components
Total Mounting ESL = L_body + L_pad_trace + L_via + L_return_path
Typical values:
L_body (0402): 0.15-0.25 nH
L_body (0201): 0.08-0.15 nH
L_pad_trace (1mm trace): 0.5-0.8 nH
L_via (single, 1.6mm board): 0.3-0.5 nH
L_via (paired power/gnd): 0.15-0.25 nH (mutual inductance cancellation)
L_return_path: depends on plane proximity
Best case (via-in-pad, paired vias, close planes):
Total = 0.15 + 0 + 0.15 + 0.05 = 0.35 nH
Worst case (trace to via, single via, far planes):
Total = 0.25 + 0.8 + 0.5 + 0.3 = 1.85 nH
Inductance Reduction Techniques
- Via-in-pad: Eliminate pad-to-via trace entirely. Via placed directly in capacitor landing pad. Requires via filling and planarization for SMT assembly.
- Multiple vias per pad: 2 vias per pad reduces via inductance by ~40% (not 50% due to mutual coupling). 3 vias gives ~60% reduction.
- Paired power/ground vias: Place VDD and GND vias adjacent (<0.5mm apart) for mutual inductance cancellation. Reduces loop inductance by 30-50%.
- Minimize via length: Use blind/buried vias connecting only to nearest plane pair. A 0.3mm blind via has ~0.1nH vs 0.4nH for through-hole via.
- Use reverse-geometry capacitors: Murata LLL series (0612 reverse) has current flow along the short axis, reducing body inductance to 0.1nH.
- Interdigitated capacitors (IDC): Multi-terminal caps like Murata LW reverse geometry reduce ESL to 0.05-0.1nH.
Reverse Geometry and Low-ESL Capacitors
| Type |
Part Example |
Body ESL |
Benefit |
| Standard 0402 |
GRM155R71C104KA88 |
0.2 nH |
Standard, widely available |
| Reverse Geometry 0204 |
Murata LLL185R70J104MA01 |
0.1 nH |
50% lower ESL |
| Multi-terminal (3-terminal) |
Murata NFM15HC104R0G3 |
0.05 nH |
75% lower ESL + filtering |
| X2Y (4-terminal) |
Johanson X2Y (500X14W104KV4) |
0.03 nH |
85% lower ESL, best performance |
Optimized mounting for FPGA BGA decoupling:
- 0201 cap with via-in-pad on both pads
- Dual vias per pad (power pad: 2x via to L2 power plane, GND pad: 2x via to L3 ground plane)
- L2-L3 plane pair spacing: 3 mils
- Total mounting ESL: 0.1(body) + 0(pad trace) + 0.1(via,dual) + 0.05(close planes) = 0.25 nH
- SRF of 100nF with this ESL: 31.8 MHz (excellent for HF range)
Poor mounting negates capacitor effectiveness:
- 0402 cap with 2mm trace to via (L_trace = 1.5nH)
- Single via through 1.6mm board (L_via = 0.5nH)
- Ground return via 3mm away (L_return = 0.8nH)
- Total mounting ESL: 0.2 + 1.5 + 0.5 + 0.8 = 3.0 nH!
- SRF of 100nF with 3nH ESL: 9.2 MHz (cap is inductive above 9MHz)
- This "100nF HF cap" only works up to 9 MHz -- mid-frequency at best!
Checkpoint 6: Via-in-Pad for Decoupling Capacitors Major
Via-in-pad (VIP) is the practice of placing vias directly within the SMD landing pads of decoupling capacitors. This eliminates the trace between pad and via, reducing mounting inductance by 0.3-1.5nH per pad. For high-frequency decoupling (above 20MHz), via-in-pad is strongly recommended and often essential.
Via-in-Pad Requirements
- Via filling: Vias must be filled with epoxy or copper to prevent solder wicking during reflow. Unfilled vias in pads cause solder voids and unreliable joints.
- Planarization: Filled vias must be planarized (flat-capped) to provide a smooth surface for solder paste printing and component placement.
- Copper capping: Best practice is to copper-plate over the filled via for reliable solder joint. Specify "via-in-pad, filled and capped" in fabrication notes.
- Via size: Use smallest practical via (0.2mm drill / 0.4mm pad for 0402 caps; 0.15mm drill / 0.3mm pad for 0201 caps).
- Aspect ratio: Maintain drill aspect ratio < 10:1 for reliable plating. For 1.6mm board: min drill = 0.16mm.
Manufacturing Considerations
Cost impact of via-in-pad:
- Standard PCB (no VIP): baseline cost
- Via-in-pad with epoxy fill: +15-25% PCB cost
- Via-in-pad with copper fill: +30-50% PCB cost
- Via-in-pad with conductive fill: +20-35% PCB cost
Break-even analysis:
If VIP eliminates one board respin due to PI issues: $50K-200K savings
VIP cost adder on 100-board prototype: $500-2000 total
Conclusion: Always use VIP for power integrity critical designs.
Fabrication Drawing Notes
NOTES FOR VIA-IN-PAD:
1. All vias within SMD pads shall be filled with non-conductive
epoxy per IPC-4761 Type VII (filled and capped).
2. Fill material: Taiyo THP-100DX1 or equivalent.
3. Planarize to within 0.5 mil of surrounding copper.
4. Copper cap plating: minimum 0.5 mil over fill material.
5. Applicable vias: All vias within 0.1mm of any SMD pad edge.
6. Via drill size for VIP: 0.2mm +/- 0.05mm
7. Finished hole size: Filled (no open hole)
Via-in-pad specification on FPGA board:
- All 200+ decoupling cap locations use VIP
- Via drill: 0.2mm, pad: 0.4mm, filled with non-conductive epoxy
- Copper capped both sides (0.5mil minimum)
- Capacitor placement: 100% first-pass yield (no tombstoning or voids)
- Impedance improvement: Average 0.6nH reduction per cap = 40% better HF performance
Unfilled vias in pads (assembly defect):
Designer placed vias in pads but didn't specify filling in fab notes.
During reflow: solder wicks down through open vias.
Result: 30% of decoupling caps have insufficient solder joints.
- Increased ESR due to poor contact: 5x nominal
- 12% caps completely open (tombstoned or floating)
- Board fails PI testing and requires 100% X-ray inspection + rework
- Not specifying fill type in fab notes: Different fill materials have different thermal properties. Conductive fill is needed for thermal vias but not for signal/power VIP.
- Via too large for pad: Via pad must fit within the component landing pad. A 0.5mm via pad in a 0.4mm cap pad will cause assembly issues.
- Assuming all fabs can do VIP: Not all fabricators support via-in-pad. Verify capability before designing. Quick-turn prototypes may not offer VIP.
- Single via in large pad: For 0805 or larger pads, use 2-3 vias per pad to maximize current handling and minimize inductance.
