Decoupling Capacitors & Target Impedance - PCB Power Integrity Guide

1. What is Decoupling?

Decoupling is the practice of providing a local energy reservoir (capacitor) close to an IC so that high-frequency transient current demands are satisfied locally, without requiring current to travel through the long, inductive path back to the voltage regulator (VRM).

VRM

IC

VDD Rail GND Load Decap Source

Current flow from VRM through power plane, with local decoupling capacitor providing high-frequency charge

The Water Tank Analogy

Think of the VRM as a water treatment plant far away from your house. The decoupling capacitor is like a water tank on your roof. When you suddenly turn on the shower (IC switching), the roof tank provides instant water pressure (current) while the plant (VRM) catches up through the long pipe (PCB trace inductance).

            Key Principle: A decoupling capacitor stores charge locally and releases it on-demand
            during fast transient events, preventing voltage droop on the power rail at the IC's power pins.
        

2. Why Decoupling Capacitors are Necessary

The Problem: Simultaneous Switching Noise (SSN)

Modern digital ICs switch millions of transistors simultaneously. Each switching event demands a burst of current from the power supply. The inductance of the power delivery path (PCB traces, vias, package leads) opposes these rapid current changes according to:

Voltage Noise Due to Inductance: V_noise = L × (dI/dt)

Where:

L = total loop inductance of the power delivery path (nH)
dI/dt = rate of change of current (A/s)

Transient current demand causes voltage droop due to PDN inductance (V = L × dI/dt)

Real-World Example

Example: STM32F7 at 216 MHz Current step: dI = 200 mA in dt = 1 ns
PDN inductance: L = 2 nH

V_noise = 2 nH × (200 mA / 1 ns) = 2 × 10^-9 × 2 × 10⁸ = 400 mV!

For a 3.3V rail with 5% tolerance (165 mV max ripple), this is unacceptable.

Without proper decoupling: The IC will experience brownouts, data corruption, clock jitter, and potentially latch-up conditions that can permanently damage the device.

3. Real Capacitor Model (ESR, ESL, SRF)

An ideal capacitor has impedance Z = 1/(2πfC) that decreases forever with frequency. Real capacitors have parasitic elements that fundamentally change their behavior at high frequencies.

ESL

Parasitic
Inductance

ESR

Series
Resistance

C

Ideal
Capacitance

Series RLC model of a real capacitor: ESL (leads/pads) + ESR (dielectric/plate loss) + C (capacitance)

ESR (Equivalent Series Resistance)

Comes from plate resistance, dielectric losses, and terminal connections
Typical values: 1-100 mΩ
Sets the minimum impedance at self-resonant frequency
Causes power dissipation: P = I²_RMS × ESR

ESL (Equivalent Series Inductance)

Comes from internal electrodes, leads, and mounting pads
Typical values: 0.3-2 nH (MLCC), 5-15 nH (electrolytic)
Dominates impedance above SRF
Smaller packages = lower ESL

Self-Resonant Frequency (SRF)

Self-Resonant Frequency: SRF = 1 / (2π × √(ESL × C))

At the SRF, the capacitive and inductive reactances cancel, leaving only ESR as the impedance. Below SRF, the component behaves as a capacitor. Above SRF, it behaves as an inductor.

Impedance vs. frequency for a real capacitor showing capacitive, resistive (ESR), and inductive (ESL) regions

Package Size	Typical ESL	Typical ESR	Best Use Frequency
0201	0.3 nH	50-200 mΩ	> 200 MHz
0402	0.5 nH	20-100 mΩ	50-300 MHz
0603	0.7 nH	10-50 mΩ	20-200 MHz
0805	1.0 nH	5-30 mΩ	5-100 MHz
1206	1.3 nH	3-20 mΩ	1-50 MHz

4. Target Impedance Concept

Target impedance is the maximum impedance that the Power Distribution Network (PDN) can present to the IC across all frequencies of interest while keeping the voltage ripple within specification. It is the single most important metric in PDN design.

            Core Idea: If the PDN impedance stays below the target impedance at all frequencies
            where the IC demands current, the voltage ripple will remain within the allowed tolerance band.
        

VRM Output Capacitors (Bulk Electrolytics)

DC - 10 kHz

PCB Bulk Decoupling (10-100 µF MLCC)

10 kHz - 1 MHz

High-Frequency Ceramic (100nF - 1µF)

1 MHz - 100 MHz

Package Capacitance + Small Ceramics (1-10nF)

100 MHz - 500 MHz

On-Die Capacitance (IC internal)

> 500 MHz

PDN hierarchy: each layer "owns" a frequency range. Together they must keep impedance below target across all frequencies.

The Frequency Domain View

The PDN is a distributed network of capacitors, inductors (traces, vias, planes), and resistors (copper resistance, ESR). At each frequency, one element dominates the impedance. The design challenge is to ensure smooth hand-off between elements with no impedance peaks exceeding the target.

Design Rule: The PDN impedance must be flat (or below target) from DC up to the highest frequency component of the IC's current signature, typically 3-5× the clock frequency.

5. Target Impedance Calculation

Target Impedance Formula: Z_target = (V_DD × Ripple%) / I_transient

Where:

V_DD = supply voltage (V)
Ripple% = maximum allowed voltage variation as a fraction (e.g., 5% = 0.05)
I_transient = maximum transient current step (A)

Worked Examples

Example 1: STM32F7 Core (1.2V) V_DD = 1.2V
Ripple = ±3% = 0.03
I_transient = 500 mA

Z_target = (1.2 × 0.03) / 0.5
Z_target = 72 mΩ

Example 2: I/O Supply (3.3V) V_DD = 3.3V
Ripple = ±5% = 0.05
I_transient = 300 mA

Z_target = (3.3 × 0.05) / 0.3
Z_target = 550 mΩ

Critical Note: Lower supply voltages have tighter target impedance! A 1.0V core with 2% ripple and 2A transient requires Z_target = 10 mΩ - extremely challenging to achieve.

Frequency Range of Interest

Maximum frequency to consider: f_max = 1 / (π × t_rise)

For STM32F7 with t_rise = 1ns:
f_max = 1 / (π × 1×10^-9) ≈ 318 MHz

The PDN must maintain impedance below Z_target from DC all the way up to f_max.

6. PDN Impedance Design Strategy

Multi-Capacitor Approach

No single capacitor can maintain low impedance across the entire frequency range. The solution is to use multiple capacitors of different values, each "owning" a portion of the frequency spectrum.

Multiple capacitor values create overlapping coverage. Combined PDN impedance (white) stays near or below target (red dashed).

Anti-Resonance Problem

When two capacitors of different values are placed in parallel, their impedance curves can create an anti-resonance peak between their individual SRFs. At this frequency, the impedance can spike above the target, creating a vulnerability.

Anti-Resonance Frequency: f_anti-res ≈ √(f_SRF1 × f_SRF2) (geometric mean of the two SRFs)

Mitigation: Use capacitors with overlapping SRFs (values no more than a decade apart) and rely on ESR damping to suppress anti-resonance peaks. The ESR actually helps here!

7. Capacitor Selection & Placement

Charging
(from VRM)

DECAP

Discharging
(to IC)

Capacitor charge/discharge cycle: charges from VRM between transients, discharges to IC during current spikes

Selection Criteria

Criterion	Consideration	Impact
Capacitance Value	Determines effective frequency range (below SRF)	Higher C = lower frequency coverage
ESL	Smaller package = lower ESL = higher SRF	Limits high-frequency effectiveness
ESR	Sets minimum impedance at SRF	Lower ESR = lower minimum Z, but less damping
Voltage Rating	Must exceed max rail voltage including transients	Use 2x derating for MLCC (DC bias effect)
Dielectric Type	X7R/X5R for decoupling, C0G/NP0 for precision	Y5V/Z5U lose 80%+ capacitance with DC bias!
DC Bias Effect	MLCC capacitance drops with applied voltage	A "10µF" X5R at rated voltage may be only 4µF

Placement Rules

Critical Placement Guidelines

Minimize loop area: Place caps as close to IC power pins as physically possible
Via placement: Use dedicated via pairs directly on the cap pads (via-in-pad preferred)
Loop inductance: The connection from cap to IC power pin adds inductance - shorter = better
Same layer: Cap and IC on same PCB side eliminates via inductance
Avoid shared vias: Each cap should have its own via pair to power/ground planes

Mounting Inductance

Total Effective Inductance: L_total = L_ESL + L_mounting + L_via

Typical values:
L_ESL (0402): 0.5 nH
L_mounting: 0.2-1.0 nH
L_via (one pair): 0.5-1.5 nH

Total: 1.2-3.0 nH typical

Electromagnetic field radiating from current loop. Smaller loop area = less radiated EMI and lower inductance.

Key Insight: A well-placed 100nF cap outperforms a poorly-placed 10µF cap at high frequencies. Placement matters more than capacitance value for frequencies above 10 MHz.

8. Practical Design Guidelines

Typical Decoupling Strategy for an MCU (e.g., STM32F7)

Location	Value	Package	Quantity	Purpose
VRM output	100-470 µF	Electrolytic/Polymer	1-2	Bulk energy storage, low-freq regulation
Near VRM	22-47 µF	0805-1210 MLCC	2-4	Mid-frequency filtering (100kHz-1MHz)
Each VDD pin	100 nF	0402	1 per pin	High-frequency decoupling (1-100MHz)
Each VDD group	4.7 µF	0402-0603	1 per 3-4 pins	Bridge between bulk and HF caps
PLL/Analog VDD	10nF + 100nF + 1µF	0402	1 each	Ultra-clean supply for sensitive analog

Number of Capacitors Needed

Minimum capacitors for target impedance: N_min = ESR_single / Z_target

Example: ESR = 5 mΩ, Z_target = 72 mΩ
N_min = 5/72 = 0.07 (1 cap sufficient at SRF)

But for broadband coverage, use:
N = ceil(I_transient × Δt / (C × ΔV_max))
(charge-based calculation for sustained transients)

Power Plane Capacitance

Closely-spaced power and ground planes form a distributed capacitor. For an FR4 dielectric with 4-mil spacing between planes:

Plane Capacitance: C_plane ≈ ε_r × ε₀ × A / d

For 1 in² area, ε_r=4.3, d=4 mil (0.1mm):
C_plane ≈ 245 pF/in²

For a 4"×4" board: ~3.9 nF total plane capacitance
Effective up to ~1 GHz (limited by plane resonance)

9. Common Mistakes

Mistakes to Avoid

Placing caps far from IC pins - adds inductance, defeats the purpose above 10 MHz
Using only one cap value - creates gaps in frequency coverage
Ignoring DC bias derating - actual capacitance may be 50% of rated value
Fan-out vias instead of via-in-pad - adds ~1 nH per via pair
Long traces from cap to via - trace adds inductance proportional to length
Using Y5V/Z5U dielectrics - lose most capacitance with temperature and DC bias
Ignoring anti-resonance - impedance peaks between cap values can exceed target
No bulk caps near VRM - VRM cannot respond fast enough without local storage

Best Practices

Simulate the PDN - use tools like HyperLynx, ANSYS SIwave, or Keysight ADS
Measure with VNA - verify PDN impedance matches simulation
Use via-in-pad - minimizes mounting inductance
Place smallest caps closest - they handle highest frequencies, need shortest paths
Check vendor SPICE models - use actual S-parameter or SPICE models for accuracy
Account for manufacturing - use ±20% tolerance in worst-case analysis
Design for the knee frequency - ensure coverage up to f_knee = 0.35/t_rise
Monitor thermal performance - high ripple current heats caps via ESR dissipation

Quick Reference: Target Impedance by Application

Application	Typical V_DD	Typical I_trans	Ripple Budget	Z_target
Low-power MCU (STM32L4)	3.3V	50 mA	±5%	3.3 Ω
High-performance MCU (STM32F7)	1.2V	500 mA	±3%	72 mΩ
FPGA Core	1.0V	5 A	±3%	6 mΩ
DDR4 SDRAM (VDDQ)	1.2V	2 A	±2.5%	15 mΩ
High-speed SerDes	0.9V	3 A	±2%	6 mΩ
Audio Codec (Analog)	3.3V	100 mA	±1%	330 mΩ

Summary: The Design Flow

Define requirements: Determine V_DD, max transient current, and ripple tolerance for each rail
Calculate target impedance: Z_target = (V_DD × Ripple%) / I_transient
Determine frequency range: DC to f_max = 1/(π × t_rise)
Select capacitor values: Choose values that provide overlapping coverage across the frequency range
Verify with models: Use vendor SPICE models to check combined impedance stays below target
Optimize placement: Minimize loop inductance with proper via and trace strategies
Simulate PDN: Full 3D EM simulation for critical designs
Measure and validate: VNA measurement on prototype to confirm impedance profile

Golden Rule of Decoupling: "The right capacitor, in the right place, at the right frequency."

Value determines WHAT frequency it covers.
Placement determines HOW WELL it covers it.
Target impedance determines WHETHER it's enough.

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