Module 2: Signal Integrity (SI)

Target impedance explicitly specified for each signal class (e.g., 50Ω single-ended, 85Ω or 100Ω differential) with reference to interface standard; documented in constraint file

2D field solver results confirm trace widths achieve target impedance on each routed layer; solver uses actual Er, copper weight, and prepreg thickness from fab stackup

Impedance tolerance specified as ±10% or tighter; manufacturing process confirmed capable of achieving this tolerance; tolerance noted on fabrication drawing

Via stub length < λ/10 at highest signal frequency OR back-drilling/blind vias specified for signals >5 Gbps; via transition modeled and impedance deviation <15% of target

Connector datasheet specifies impedance within ±10% of PCB trace target; mating interface impedance profile verified via S-parameter data or TDR measurement

Trace width changes (BGA breakout, connector fanout) are tapered over ≥3x trace width distance; impedance deviation at transition <10% per simulation or calculation

Er and loss tangent values used in impedance calculations are from laminate manufacturer data at the signal frequency of interest (not just 1 MHz value); Dk variation with frequency accounted for

Copper roughness modeled (Hammerstad-Jensen or Huray) for signals >5 Gbps; additional loss due to roughness quantified and included in loss budget; low-profile copper specified if needed

Differential pairs maintain constant spacing (gap ±10%) throughout entire route; intra-pair length mismatch <5 mils; no single-ended segments except at component pads

Test coupons defined on fabrication panel for each impedance class (SE and differential); coupon structures match actual trace geometry and stackup layers used in design

Termination scheme (series, parallel, Thevenin, AC, on-die) selected based on topology, data rate, and power constraints; choice justified against interface specification requirements

Series resistor value = Z0 - R_driver_output (±20%); total source impedance (R_driver + R_series) matches trace Z0 within 10%; verified against driver IBIS model output impedance

Parallel termination resistor placed within 150 mils of receiver pin; no stub or via between termination and receiver input; return path via adjacent to resistor pad

Resistor tolerance ≤1% for impedance-critical terminations; worst-case mismatch (including tolerance) produces reflection coefficient <5% at receiver

DC power consumed by parallel terminations calculated (P = V^2/R per line); total termination power within supply current budget and resistor power rating with ≥50% derating

Signal topology (point-to-point, star, daisy-chain, fly-by) matches interface specification for data rate; multi-drop loads do not exceed driver fan-out or degrade signal below receiver threshold

All routing stubs (T-junctions, component pads, test points) shorter than 1/10 of signal rise time equivalent wavelength; stubs >limit eliminated or compensated

DDR ODT values configured per JEDEC spec for actual topology (rank count, loading); write/read ODT settings independently verified; RTT_NOM, RTT_WR, RTT_PARK all specified

AC coupling cap value gives f_low < 100 kHz (or per spec); self-resonant frequency > signal Nyquist; capacitor ESL and pad geometry do not create impedance discontinuity >10%

Differential pairs have common-mode termination (resistor to ground at midpoint or dedicated CM choke) where interface spec requires it; CM rejection verified to meet EMC requirements

High-speed signal spacing ≥3x trace width (3W rule) or per crosstalk simulation; spacing constraints entered in EDA tool and DRC passes with zero violations

NEXT coefficient <5% of signal amplitude (or per interface spec) for worst-case aggressor/victim pair; verified by simulation or calculation for coupled length

FEXT within noise budget for stripline (<2% for tightly coupled) and microstrip configurations; FEXT calculated using actual coupled length and spacing

Grounded guard traces with vias every λ/10 placed between sensitive signals where spacing alone is insufficient; guard trace grounded at both ends and intermediate points

Adjacent signal layers routed orthogonally (90°) to minimize broadside coupling; or separated by ≥2x dielectric thickness if parallel routing required

Worst-case simultaneous switching aggressor scenario analyzed (all adjacent nets switching together); victim noise remains below receiver noise margin with ≥20% margin

Maximum parallel coupled length between adjacent high-speed traces limited per crosstalk budget (typically <500 mils for >1 Gbps signals at minimum spacing); enforced via design rules

Clock traces isolated from data signals by ≥5x trace width or on separate layer with ground plane between; no parallel data traces within coupling distance for >100 mils

Connector pinout has ground pins between each signal or signal pair; ground-to-signal ratio ≥1:2 for high-speed interfaces; no adjacent pins carry signals that switch simultaneously

Full 3D or 2.5D crosstalk simulation completed for all critical net groups; results document NEXT and FEXT are within interface noise budget at actual routed geometry

Setup and hold times met at receiver with positive margin across all PVT corners (process/voltage/temperature); margin ≥10% of clock period or per interface spec

Propagation delay through complete channel (trace + connectors + packages + vias) calculated for each signal; delay values documented and used in timing budget

Differential pair P/N length mismatch <5 mils for >5 Gbps links (or per spec); skew <10% of unit interval; verified in layout tool with length-match report

All data bus signals length-matched within specification (e.g., ±25 mils for DDR DQ-DQS, ±100 mils for address/command); constraint manager shows zero violations

Clock and associated data signals have controlled relative delay; clock arrives within valid data window at receiver accounting for all delay elements including buffers and package delays

Length matching constraints documented per interface with specific tolerances (in mils or ps); constraints entered in EDA constraint manager and all nets pass DRC

Length-matching meanders use amplitude ≥3x trace width and spacing ≥3x trace width to avoid self-coupling; meander segments do not create impedance discontinuities >5%

Via transitions included in propagation delay calculations (typical 10-15 ps per via); layer changes counted for each net and delay added to total flight time

Propagation delay variation over operating temperature range (±50 ppm/°C typical for FR4) analyzed; timing budget includes worst-case temperature-induced skew

Eye diagram analysis (simulated or measured) shows eye height ≥interface mask + 20% margin and eye width ≥0.3 UI at BER target; no mask violations at worst-case corner

Every high-speed signal trace has a continuous, unbroken reference plane (GND or power) on the immediately adjacent layer for the entire route length; verified by visual inspection or CAD query

No high-speed signal crosses a power plane split, void, or cutout in its reference plane; DRC rule flags any such crossing; all violations resolved or mitigated with stitching

Ground stitching vias placed within 50 mils of every signal via that transitions layers; at least one return via per signal via; return via connects both reference planes

When signal changes reference from one plane to another, a stitching capacitor (100 nF) or direct via connects the two reference planes within 50 mils of the signal via

Via anti-pads (clearance holes in planes) do not create gaps wider than 3x trace width in the return path for adjacent high-speed traces; anti-pad size minimized to design rule minimum

No high-speed signal routes across different power domain boundaries without a stitching capacitor or dedicated return path; all crossings documented with mitigation approach

Return current path verified for all critical nets using EDA current density analysis or manual review; no forced detour >3x trace width around obstacles in return plane

Total voiding (from vias, routing, cutouts) in ground reference plane <20% under high-speed signal areas; impedance impact of voiding analyzed and within tolerance

Total channel insertion loss (PCB trace + connectors + vias + AC caps) at Nyquist frequency documented and within receiver equalization capability; margin ≥2 dB below RX limit

S21 magnitude meets channel specification at Nyquist frequency (e.g., PCIe Gen4: <-20 dB at 8 GHz); IL profile monotonically increasing with frequency (no resonance dips)

S11 and S22 better than -10 dB (or per specification) across entire signal bandwidth; no resonant peaks above the limit; verified at both TX and RX reference planes

Insertion loss deviation from best-fit line <±0.5 dB (or per spec) across signal bandwidth; deviations indicate resonances that must be identified and resolved

Integrated crosstalk noise (ICN) within specification budget; ICN/IL ratio (ICR) meets channel compliance at target data rate; measured/simulated with all adjacent aggressors active

Transmitter pre-emphasis/de-emphasis (pre-cursor and post-cursor taps) configured to compensate for channel loss; settings validated via channel simulation to achieve target eye opening

Receiver CTLE and DFE capability sufficient for channel impairments; simulated equalized eye meets BER target (e.g., 1e-12) with ≥10% margin on eye height and width

AC cap value per interface spec (e.g., 100 nF for PCIe); SRF > 2x Nyquist frequency; low-ESL package (0201/0402); placed symmetrically on P and N within 100 mils of TX pins

Back-drilling or blind/buried vias used for all signals >5 Gbps; residual stub <8 mils after back-drill; stub resonance frequency confirmed >2x Nyquist

Reference clock total jitter (RJ + DJ) meets interface spec at target BER (e.g., PCIe: <3 ps RMS for Gen4 common clock); clock source datasheet confirms compliance

Multi-lane link lane-to-lane skew within interface specification (e.g., PCIe: <20 ns between any two lanes in a link); length difference between lanes documented and compliant

BGA breakout maintains target impedance (±10%) through escape vias and neck-down region; via stubs in breakout addressed; differential pair symmetry maintained through breakout

DDR topology (fly-by for DDR3/4/5, T-branch for DDR2) matches controller and JEDEC requirements for generation and rank count; topology documented with routing order

Data (DQ) to strobe (DQS) length match within ±25 mils (or per controller spec) per byte lane; all 8 DQ bits within a byte lane matched to their associated DQS pair

Address, command, and control signals routed in fly-by order (controller to DRAM0 to DRAM1...); skew between address lines within ±100 mils; total propagation delay within controller budget

Memory controller confirmed to support write leveling for fly-by topology; per-byte-lane DQS delay adjustment range sufficient for maximum fly-by propagation skew

VTT regulator sized for worst-case termination sink/source current (all lines switching); VTT = VDDQ/2 ±2%; regulator can both sink and source current; decoupling per JEDEC

VREF generated correctly: DDR3 external divider (0.5x VDDQ ±0.5%); DDR4/5 internal training mode enabled; VREF decoupling ≥1 μF within 100 mils of each DRAM VREF pin

On-die termination values (RTT_NOM, RTT_WR, RTT_PARK) correctly set for actual topology and rank count; values validated by SI simulation showing compliant eye at receiver

IBIS or IBIS-AMI simulation completed for actual layout extraction; eye diagrams for read and write pass JEDEC mask at worst-case PVT corners for all byte lanes

VDDQ, VPP, and VTT supplies have filtering per JEDEC: bulk (≥47 μF) + mid (≥4.7 μF) + local (100 nF per DRAM); ripple <1.5% of nominal; decoupling placed within 100 mils of each power pin

DQ trace impedance meets JEDEC target (DDR4: 40Ω ±10% single-ended; DDR5: 40Ω ±10%); impedance verified by field solver for actual stackup and trace geometry on routed layer

Voltage reference has dedicated filtering (10 Ω + 10 μF + 100 nF minimum); reference trace isolated from digital switching noise by ≥50 mils or separate layer; reference noise <LSB/2

Analog ground strategy defined and implemented: single-point connection (star ground) or controlled split with connection under ADC/DAC; no digital return current flows through analog ground area

PCB-induced noise (crosstalk + PDN ripple + EMI pickup) <1/2 LSB of ADC; total system SNR degradation from PCB <1 dB below theoretical limit for the converter resolution

Anti-aliasing filter -3 dB bandwidth ≤ Fs/2; attenuation at Fs ≥ADC resolution (e.g., ≥72 dB for 12-bit); filter topology and component values verified by simulation

Signal conditioning (gain, offset, filtering) correctly scales sensor output to ADC input range; gain error <0.1% and offset error <1 LSB over temperature; bandwidth matches sensor specification

High-impedance analog inputs (>1 MΩ) have guard rings driven at input potential (or ground) on all PCB layers; guard ring surrounds input trace and component pads; leakage current <1 nA

Dissimilar metal junctions minimized in precision measurement paths (<1 μV/°C required); symmetric layout ensures thermal EMF cancellation; no copper-solder-copper transitions in signal path where ΔT exists

IBIS or IBIS-AMI models available and validated for all high-speed drivers and receivers; model version matches silicon revision; models include package parasitics (RLC)

Pre-layout SI simulation performed to validate topology, termination strategy, and define routing constraints; results document achievable eye opening and required trace length limits

Post-layout extraction (2.5D or 3D EM) and simulation completed for all critical interfaces; extracted model includes actual trace geometry, vias, and discontinuities; eye diagrams pass compliance masks

S-parameters extracted for all connectors, via transitions, and critical discontinuities; frequency range covers DC to ≥3x Nyquist; passivity and causality verified on extracted models

Simulated or measured eye diagrams pass interface compliance mask with zero violations at target BER; both voltage and timing margins documented for each lane

Time-domain reflectometry (TDR) analysis performed on critical channels; impedance profile within ±10% of target along entire length; discontinuities identified and root-caused

Total jitter (DJ + RJ) at target BER (e.g., 1e-12) within interface budget; jitter components decomposed and dominant contributor identified; DJ <0.3 UI and RJ <specified RMS limit

SI simulation includes PDN model to account for SSN (simultaneous switching noise); combined SI+PI analysis shows signal quality still meets spec under worst-case switching activity