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Module 1: Schematic Review

Comprehensive checklist for schematic design verification

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1.1 Schematic Reviewer Tool

Upload and analyze schematic PDFs with the interactive Schematic Reviewer. Extracts components, power networks, open signals, and generates review reports.

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1.2 General Schematic Quality View Tutorial

Hierarchical structure
Schematic organized into functional blocks with clear hierarchy; each block fits on one sheet
Major
Sheet numbering & title blocks
All sheets numbered sequentially; title block contains project name, revision, date, author, and approver fields
Minor
Net naming convention
All nets use consistent naming (e.g., VCC_3V3, SPI0_CLK, USB_DP); no default/auto-generated names on intentional nets
Major
Reference designators
Unique sequential ref-des per type (R1,R2..C1,C2..U1,U2); no duplicates; annotation matches physical grouping
Major
No floating pins
Every IC pin is either connected to a net or explicitly marked as NC (No Connect); zero unintended floating pins
Critical
Power/ground symbols consistent
Same voltage rail uses same symbol throughout; no ambiguous ground symbols; each rail clearly distinguishable
Critical
Off-sheet connectors match
Every off-sheet connector label exists on exactly two sheets; names match exactly (case-sensitive); no orphans
Major
ERC clean (zero errors)
Electrical Rules Check passes with 0 errors; all warnings reviewed and either fixed or documented as acceptable
Critical
Component values displayed
All passives show value+tolerance (e.g., 100nF/X7R/10%); ICs show manufacturer part number; no missing values
Major
Junction dots & wire clarity
All 4-way junctions have dots; no ambiguous crossings; wires don't overlap without connecting
Minor
Bus notation correct
Buses labeled with bit ranges [7:0]; individual signals named within bus; bus members resolvable
Major

1.3 Power Architecture & Distribution View Tutorial

Power tree documented
Complete power tree showing: input source → all regulators → all loads; includes enable dependencies and sequencing
Critical
Input voltage range verified
Input supply min/max matches connector rating AND first-stage regulator input range with ≥10% margin
Critical
Regulator headroom adequate
LDO: (Vin_min - Vout) > dropout voltage at max load and max temp; Buck: duty cycle achievable
Critical
Power budget calculated
Total power for each mode (sleep/idle/active/peak) calculated; sum < supply capability with ≥20% margin
Critical
Voltage sequencing correct
Power-up order matches ALL IC datasheet requirements (typically: core → I/O → peripherals); no violations
Critical
Enable/PGOOD chain correct
PGOOD of upstream regulator drives ENABLE of downstream; chain implements correct sequence; no race conditions
Critical
Inrush current managed
Peak inrush at power-on below connector/fuse rating; soft-start configured or NTC/active limiter present
Major
Reverse polarity protection
Input has reverse polarity protection (P-MOSFET, ideal diode, or Schottky); survives reversed input without damage
Critical
Overcurrent protection
Fuse or eFuse sized: rated current > max operating; blow/trip current < wire/trace damage threshold
Critical
Overvoltage protection
TVS/varistor clamping voltage: above max operating voltage but below absolute max of downstream components
Major
Feedback resistors verified
Vout = Vref × (1 + R1/R2) calculated and matches target ±1%; resistor values from datasheet recommended range
Critical
Loop compensation correct
Compensation network values match datasheet/app-note for selected inductor and output capacitor; phase margin >45°
Critical
Switching frequency appropriate
Fsw chosen to balance efficiency (lower) vs. size (higher); not on frequency that creates EMI at sensitive bands
Major
Input/output capacitor ESR
Cap ESR within regulator's stable ESR range (check datasheet stability region); not too high or too low
Critical

1.4 Decoupling & Bypass Capacitors View Tutorial

Every power pin decoupled
Each VCC/VDD pin on every IC has a dedicated local decoupling capacitor (100nF minimum); no pins missed
Critical
Bulk capacitors at entry points
10-100µF bulk cap within 10mm of each power entry point and regulator output; provides energy reservoir
Major
Values match IC datasheet
Decoupling values (capacitance, quantity, type) exactly match or exceed IC manufacturer recommendations
Critical
Multi-value decoupling for high-speed
High-speed ICs (FPGA, processor, DDR) use cascaded values (e.g., 10µF + 1µF + 100nF + 10nF) per datasheet
Major
Ferrite bead isolation
Analog/RF/PLL power pins isolated from digital via ferrite bead; bead impedance >100Ω at noise frequency
Major
Voltage rating ≥2× operating
Ceramic cap rated voltage ≥ 2× operating voltage (accounts for DC bias derating); electrolytics ≥1.5×
Critical
DC bias derating accounted for
Effective capacitance at operating voltage checked from manufacturer curves; X5R/X7R may lose 50-80% at rated V
Major
Temperature rating adequate
Capacitor dielectric rated for full operating range (X7R: -55 to +125°C; X5R: -55 to +85°C); matches environment
Major

1.5 Component Selection & Specifications View Tutorial

Operating temperature range
Every component's rated temperature covers product operating range with margin; no commercial-grade parts in industrial designs
Critical
Voltage/current ratings with margin
Worst-case voltage ≤80% of rating; worst-case current ≤70% of rating; verified at temperature extremes
Critical
Power dissipation within rating
P_actual < P_rated × derating factor at max ambient; thermal resistance × power < allowable temp rise
Critical
Tolerance analysis done
Critical circuits (voltage dividers, filters, references) analyzed for worst-case tolerance stack-up; still meets spec
Major
Availability & lifecycle active
All components verified as "Active" status (not NRND/Obsolete); available from ≥2 authorized distributors
Major
Second source identified
All critical/single-source components have a qualified alternate (same specs, compatible footprint) documented
Major
Footprint matches package
Library footprint verified against component datasheet (pad dims, pitch, pin 1 orientation); IPC-7351 compliant
Critical
RoHS/REACH compliant
All components and PCB materials verified RoHS compliant; no SVHC above threshold; documentation available
Major
Inductor saturation current
I_sat > I_peak_max × 1.3; checked at max operating temperature (saturation current decreases with temp)
Critical
Crystal load capacitance
CL_board = (C1×C2)/(C1+C2) + C_stray matches crystal specified CL within ±5%; C_stray estimated 2-5pF
Critical

1.6 Connectivity & Net Verification View Tutorial

Pin-to-pin vs datasheet
Every IC pin connection cross-checked against datasheet pin table; signal names and pin numbers match 100%
Critical
Pull-ups on open-drain outputs
All open-drain/collector outputs have pull-up to appropriate rail; R value gives adequate rise time for bus speed
Critical
I2C pull-up values correct
R_pullup gives: t_rise < 0.3×t_period AND I_sink < 3mA per device; typical 2.2-4.7kΩ for 400kHz
Major
No I2C/SPI address conflicts
Every device on each I2C bus has unique 7-bit address; address pins configured correctly; no overlaps
Critical
Unused inputs terminated
ALL unused digital inputs tied to VCC or GND (per datasheet recommendation); no floating CMOS inputs anywhere
Critical
Level translation present
Bidirectional level translators between all different voltage domains (e.g., 1.8V↔3.3V); direction control correct
Critical
Drive strength sufficient
Output I_OH/I_OL > load requirements (fan-out × I_IH/I_IL); bus capacitance within driver capability
Major
Test points on critical nets
Test points placed on: all power rails, reset, clock, UART debug, key data buses; accessible for scope probes
Minor

1.7 Interface Circuits View Tutorial

USB circuit compliant
USB has: 90Ω diff pair, correct pull-ups (1.5kΩ for FS), ESD on D+/D-, VBUS detection, proper termination per spec version
Critical
Ethernet magnetics correct
Transformer matches PHY (turns ratio, isolation, CT connection); Bob Smith termination if required; correct MDI pinout
Critical
UART TX/RX crossover correct
TX of device A connects to RX of device B and vice versa; DTE/DCE roles identified; flow control connected if used
Critical
DDR interface complete
DDR has: correct topology, VTT termination, VREF, ODT config pins, proper decoupling per JEDEC; all byte lanes connected
Critical
Differential pair AC coupling
AC coupling caps on diff pairs where required (PCIe, SATA, USB3); value gives f_low < 100kHz; matched between P and N
Critical
CAN bus termination
120Ω termination at each end of CAN bus; split termination (2×60Ω + cap) for CM filtering if applicable
Critical

1.8 Protection Circuits View Tutorial

ESD on all external I/O
Every user-accessible port has TVS/ESD diode; placed at connector, before any other component in signal path
Critical
TVS clamping < IC abs max
TVS V_clamp at I_PP < IC absolute maximum voltage rating with margin; verified at peak pulse current
Critical
ESD capacitance acceptable
TVS parasitic capacitance < signal bandwidth allows (e.g., <0.5pF for USB3, <5pF for USB2, <50pF for UART)
Major
Latch-up prevention
No I/O pin can be driven above VCC+0.3V or below GND-0.3V during any power state (including sequencing)
Critical
Hot-plug protection
Hot-pluggable interfaces have: current limiting, sequencing control, and pre-charge of bus capacitance
Critical
Surge protection (power port)
Power input survives IEC 61000-4-5 surge at target level; MOV/TVS energy rating > expected surge energy
Critical

1.9 Clock & Oscillator Circuits View Tutorial

Load capacitors calculated
CL = (C1×C2)/(C1+C2) + Cstray matches crystal spec ±10%; Cstray estimated from layout (2-5pF typical)
Critical
Drive level within spec
Crystal drive level (µW) within manufacturer specification; excessive drive causes aging/damage
Major
Frequency stability sufficient
Total freq error (initial + aging + temperature) < interface requirement (e.g., ±50ppm for USB, ±25ppm for Ethernet)
Critical
PLL loop filter designed
PLL loop filter bandwidth and component values match IC recommendation; phase margin > 50°; lock time adequate
Critical
Clock jitter within budget
Total jitter (RJ+DJ) at clock output < interface spec (e.g., PCIe: 1ps RMS; USB3: 1.5ps RMS for ref clock)
Critical

1.10 Reset & Supervisory Circuits View Tutorial

POR timing adequate
Reset held active until: all supplies stable + clocks running + datasheet min reset pulse width met (typically >1ms)
Critical
Supervisor threshold correct
Threshold voltage = supply nominal × (1 - tolerance); detects before IC minimum operating voltage reached
Critical
Brownout detection
Voltage monitor detects supply dip below IC minimum and asserts reset; hysteresis prevents oscillation
Critical
Watchdog timer present
Hardware watchdog IC (or internal WDT enabled) resets system on firmware hang; timeout appropriate for application
Major
All devices reset connected
Every IC requiring reset is connected to appropriate reset network; reset polarity (active-high/low) matches
Critical

1.11 Connectors & Mechanical View Tutorial

Pinout vs mating connector
Connector pinout verified against mating connector/cable; gender and orientation (top/bottom view) confirmed
Critical
Keying/polarity protection
Connector has mechanical keying or asymmetric pinout preventing incorrect mating orientation
Major
Pin current rating adequate
Each pin current rating > max current through that pin × 1.5 derating; multiple pins paralleled for high current
Critical
Ground pins sufficient
Number of ground return pins adequate for signal return current; ground-signal ratio appropriate for speed
Major

1.12 Documentation & Annotation View Tutorial

BOM complete & accurate
Every schematic component in BOM with: MPN, description, value, footprint, quantity; quantities match schematic count
Critical
Design calculations noted
Critical calculations annotated (regulator Vout formula, filter cutoff, timing); enables future review without re-derivation
Minor
DNP/variants marked
Do-Not-Place components and board variants clearly marked; variant BOM documented separately
Major
Revision history maintained
Change log on schematic lists all changes per revision with date and author; current revision clearly shown
Minor
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