Module 1.11 - Documentation
Ensuring complete, accurate documentation for manufacturing, assembly, and maintenance
Ensuring complete, accurate documentation for manufacturing, assembly, and maintenance
The Bill of Materials (BOM) is the complete list of every component required to assemble the PCB. It must include: reference designator, manufacturer part number (MPN), description, value, package/footprint, quantity, and approved alternatives. Every component on the schematic must appear in the BOM, and every BOM entry must correspond to a component on the schematic. Zero discrepancies are acceptable.
The BOM is the primary procurement and assembly document - errors here directly become physical errors on boards.
A BOM error results in wrong parts being ordered and assembled onto boards. A missing MPN means the purchaser guesses (wrong package, wrong value, wrong voltage rating). A wrong quantity means boards are partially assembled. A missing component means an empty pad that must be reworked ($5-$50 per board in production). BOM errors are caught only at electrical test - after all assembly labor is spent. In worst case, wrong parts pass test initially but fail in the field (wrong temperature grade, insufficient voltage rating).
Complete BOM entry example:
+------+--------------------+---------------------------+-------+--------+-----+ | Ref | MPN | Description | Value | Pkg | Qty | +------+--------------------+---------------------------+-------+--------+-----+ | C1 | GRM155R71C104KA88J | Cap Ceramic 100nF 16V X7R | 100nF | 0402 | 1 | | C2-5 | GRM155R71C104KA88J | Cap Ceramic 100nF 16V X7R | 100nF | 0402 | 4 | | R1 | RC0402FR-0710KL | Res 10k 1% 1/16W | 10k | 0402 | 1 | | U1 | STM32F407VGT6 | MCU ARM Cortex-M4 168MHz | - | LQFP100| 1 | | Y1 | NX3225SA-8M00000 | Crystal 8MHz 8pF 20ppm | 8MHz | 3225 | 1 | | J1 | 12401610E4#2A | Conn USB-C Receptacle SMD | - | USB-C | 1 | +------+--------------------+---------------------------+-------+--------+-----+ Alt sources documented: C1-5 Alt: Samsung CL05B104KO5NNNC (verified equivalent) R1 Alt: Yageo RC0402FR-0710KL (exact equivalent)
Incomplete BOM:
+------+------------+------------------+-------+-----+ | Ref | MPN | Description | Value | Qty | +------+------------+------------------+-------+-----+ | C1-20| (see note) | 100nF capacitor | 100nF | 20 | <-- No MPN! What package? What voltage? | R?? | TBD | Resistor | ?? | 3 | <-- Unassigned, value unknown | U1 | STM32F4xx | Microcontroller | - | 1 | <-- Which STM32F4?? Dozens of variants! | J1 | (generic) | USB connector | - | 1 | <-- Which type? A? B? C? Receptacle? Plug? +------+------------+------------------+-------+-----+ Note: "Use standard 100nF caps" -- What package? Voltage? Dielectric? Manufacturer? Missing: test points, fiducials, mounting hardware
KiCad: Use Symbol Fields Table (Edit > Symbol Fields) to bulk-edit all component fields. Export BOM with KiBOM or Interactive BOM plugin. Verify MPN field populated for every component.
Altium: ActiveBOM provides real-time BOM management with live pricing and availability. Use BOM comparison tool to verify schematic-to-BOM consistency. Report > Bill of Materials.
OrCAD: Use BOM report generator (Reports > Bill of Materials). CIS (Component Information System) integrates with supplier databases for MPN validation. Cross-reference with PCB component list.
Assembly notes are instructions placed directly on the schematic that communicate critical information to the assembly house: component orientation requirements, special handling procedures, soldering parameters, test procedures, and configuration-specific population. These notes supplement the BOM and assembly drawings by providing context that raw data cannot convey. They are particularly important for non-standard components, sensitive devices, and configuration options.
Assembly notes on the schematic ensure critical information travels WITH the design, not in separate documents that get lost.
Without assembly notes: the assembly house guesses component orientation for non-standard packages, uses standard reflow profile for temperature-sensitive components, populates debug-only components in production builds, and handles moisture-sensitive parts without precaution. Each missing note is a potential assembly defect. At $3-$10 per rework touch, 100 boards with 3 defects each = $900-$3000 in rework costs plus schedule delay. Clear notes prevent these entirely.
Assembly notes on power supply sheet:
ASSEMBLY NOTES - POWER SUPPLY SECTION: 1. D1 (Schottky diode): Cathode band orientation per PCB silkscreen marking. 2. C15 (47uF electrolytic): Positive terminal toward R12 (silkscreen + marking). 3. U2 (TPS62130 QFN): Exposed thermal pad MUST be soldered to ground pour. Use solder paste stencil aperture per manufacturer recommendation (60% coverage). 4. L1 (2.2uH power inductor): No component height restriction - 3mm max height OK. 5. R8/R9 (feedback divider): Use 1% tolerance ONLY. Do NOT substitute 5% parts. 6. Variant A (3.3V output): Populate all components as shown. Variant B (5.0V output): Substitute R8=20k, R9=10k. Change C10 to 22uF/10V. 7. MSL NOTE: U2 is MSL-3. Track floor life from moisture barrier bag opening.
No assembly notes: Schematic has no text notes. BOM lists components but provides no assembly guidance. Assembly house: (1) Orients D1 diode randomly (50% chance backwards). (2) Uses maximum reflow temperature profile (damages temperature-sensitive crystal). (3) Does not solder thermal pad on QFN (regulator overheats). (4) Populates debug-only 0-ohm resistors in production (changes board behavior). Total defect rate: 15% on first production run. All boards require inspection and selective rework.
KiCad: Use Place > Text for assembly notes. Place notes prominently on relevant schematic sheets. Include in PDF print output. Use text boxes for grouping related notes.
Altium: Use Text Frames for assembly notes. Include in schematic print output and smart PDF. Notes can be linked to specific components or regions.
OrCAD: Place text annotations on schematic pages. Include in print/PDF output. Use standardized note formatting for consistency across projects.
Variant management handles multiple product configurations from a single PCB design. Different variants may have: different component populations (DNP certain parts), different component values (different feedback resistors for different output voltages), different firmware loads, or different connector configurations. All variants must be clearly documented with a variant table showing exactly which components are placed for each configuration.
This is essential when a single PCB serves multiple products or regional configurations (voltage, frequency, features).
Without clear variant documentation, the assembly house builds all boards identically (either all components populated, or random selection). Variant errors are discovered only during functional testing (if caught) or by the customer (expensive). A board built as "Variant A" but requiring "Variant B" configuration may need 10-20 component changes in rework - often more expensive than scrapping and rebuilding. Clear variant management eliminates this waste entirely and enables flexible manufacturing from common PCB stock.
Variant management table:
VARIANT TABLE - Smart Sensor Hub +----------+------------------+---------+---------+---------+ | Ref Des | Base (WiFi+BLE) | Var A | Var B | Var C | | | | (WiFi) | (BLE) | (LoRa) | +----------+------------------+---------+---------+---------+ | U5 (WiFi)| ESP32-WROOM-32E | Populate| DNP | DNP | | U6 (BLE) | nRF52832 | DNP | Populate| DNP | | U7 (LoRa)| SX1276 | DNP | DNP | Populate| | R20-R23 | WiFi matching | Populate| DNP | DNP | | R24-R27 | BLE matching | DNP | Populate| DNP | | R28-R31 | LoRa matching | DNP | DNP | Populate| | L2 (ant) | 2.4GHz matching | Populate| Populate| DNP | | L3 (ant) | 868MHz matching | DNP | DNP | Populate| | J3 (ant) | U.FL (2.4GHz) | Populate| Populate| DNP | | J4 (ant) | SMA (868MHz) | DNP | DNP | Populate| +----------+------------------+---------+---------+---------+ Each variant has separate BOM output file for manufacturing. PCB has silkscreen area for variant label sticker.
Undocumented variants: Engineer knows that "to make the 5V version, change R3 to 33k and remove C7." This information exists only in the engineer's memory. When they are on vacation, production builds 500 units of the wrong variant. Discovery happens 2 weeks later during customer acceptance testing. 500 boards must be reworked (R3 replaced + C7 removed): cost = 500 * $15 rework + $2000 expedite shipping = $9,500 total. All preventable with a variant table.
KiCad: Use component fields (e.g., "Variant" field) to mark DNP status. KiCad 7+ supports variants in schematic. Generate variant-specific BOMs with scripting or plugins.
Altium: Native Variant Management: Project > Variants. Define base design and variant-specific changes. Generates separate BOM, assembly drawings, and pick-place per variant automatically.
OrCAD: Use variant manager in CIS. Define configurations with different component populations. Generate variant-specific outputs for manufacturing.
Revision history is a formal log of all changes made to the schematic across design iterations. It records: revision letter/number, date, author, description of changes, reason for change (ECO reference), and affected components/sheets. The current revision in the title block must match the latest entry in the revision history. This provides full traceability of the design evolution from initial concept through production.
In regulated industries (medical, automotive, aerospace), revision history is a legal requirement and audit item.
Without revision history: nobody knows what changed between Rev B and Rev C, making it impossible to determine if a specific board revision includes a critical fix. When a field failure occurs, engineers cannot determine which revision introduced the problem or which units are affected (was the fix in Rev C or Rev D?). For regulated products, missing revision history means the design documentation is uncontrolled - this fails regulatory audits (ISO 13485, IATF 16949, AS9100) and can result in product recall.
Complete revision history:
REVISION HISTORY - Smart Sensor Hub (PCB-2024-001) +-----+------------+----------+-----------------------------------------------+ | Rev | Date | Author | Description | +-----+------------+----------+-----------------------------------------------+ | A | 2024-01-15 | J.Smith | Initial release for prototype | | B | 2024-03-02 | J.Smith | ECO-2024-012: Fix USB enumeration failure | | | | | - Changed R5 from 1.5k to 22R (USB DP pull-up)| | | | | - Added C18 100nF to VBUS for stability | | | | | - Corrected U1 pin 45 connection (was floating)| | C | 2024-04-18 | M.Lee | ECO-2024-019: Production optimization | | | | | - Changed C1-C12 from 0402 to 0603 (assembly) | | | | | - Added TP5-TP8 test points for production | | | | | - Updated J2 connector to new supplier MPN | +-----+------------+----------+-----------------------------------------------+ Current revision: C (matches title block on all sheets)
No revision history: Title block shows "Rev D" but there is no revision history document anywhere. Nobody knows what Rev A, B, C, or D changed. A field failure is traced to a specific component - but which board revision has the fix? Production is building Rev D, but the fix might have been in Rev C (requiring recall of Rev A/B only) or might be unfixed (all revisions affected). Without history, engineering must manually compare netlists of all revisions - taking days instead of minutes.
KiCad: Add revision history as text frame on sheet 1. Update revision field in File > Page Settings. Use git commits for detailed change tracking alongside schematic revision marks.
Altium: Use built-in revision management (Altium 365/Vault). Document changes in schematic text frame. Project history tracks all modifications automatically.
OrCAD: Add revision history table on first schematic page. Update Design Properties for revision tracking. Use ECO (Engineering Change Order) process for formal change management.
Design notes explain the "why" behind non-obvious circuit choices directly on the schematic. They document: design equations (feedback divider ratios, filter cutoff calculations), component selection rationale (why this specific part and not the obvious alternative), operating constraints (maximum duty cycle, minimum load for stability), and any circuit behavior that would not be obvious to another engineer reviewing the design. These notes preserve design knowledge that would otherwise be lost when the original designer moves to another project.
If a competent engineer would ask "why is this done this way?" - there should be a note explaining it.
Without design notes, the next engineer who touches the design (or the original engineer 6 months later) will not understand the design rationale. They may "optimize" a component value that was carefully chosen for stability, remove a "unnecessary" resistor that was actually critical for oscillator startup, or change a capacitor to a cheaper type that doesn't meet the ESR requirement. Design notes prevent these well-intentioned "improvements" that break the design. They also dramatically speed up debugging by explaining expected behavior.
Well-annotated voltage regulator circuit:
Notes on schematic near TPS62130 circuit:
"OUTPUT VOLTAGE SETTING:
Vout = Vref * (1 + R_top/R_bot) = 0.8V * (1 + 31.6k/10k) = 3.328V
Tolerance analysis: With 1% resistors, worst case: 3.278V to 3.379V
STM32 requirement: 3.0V to 3.6V. PASS.
COMPENSATION: Internal Type-III. Stable with ESR < 50mOhm on output cap.
Selected caps: 2x 22uF X5R (ESR ~3mOhm). See TPS62130 datasheet Figure 23.
SOFT-START: Internal 1ms. Inrush current limited by soft-start.
External SS cap: none required (internal sufficient for this load).
MINIMUM LOAD: 0mA (pulse-skipping mode below 10mA - acceptable for this design).
EMI NOTE: At light load, switches to PFM mode. Switching frequency varies 100kHz-2MHz.
If EMI-sensitive, keep load > 10mA to force PWM mode (continuous switching).
EFFICIENCY: 92% at 500mA, 88% at 100mA, 78% at 10mA (PFM mode)."
No design notes: Complex compensation network on a switching regulator: R_comp = 4.7k, C_comp = 2.2nF, C_high = 47pF. No explanation of why these values were chosen. New engineer "cleans up" the design - removes C_high (thinks it's a leftover from prototype rework). Regulator now has insufficient phase margin at high output current. Board oscillates at 500kHz with 200mV ripple when load exceeds 1.5A. Takes 2 weeks of debugging to discover the missing 47pF capacitor was a critical stability component.
KiCad: Use Place > Text for design notes. Place near the relevant circuit elements. Use different text size to distinguish notes from component labels.
Altium: Use Text Frames and annotations. Can link to external documents. Notes survive schematic edits without being accidentally moved.
OrCAD: Use schematic text annotations. Group notes with borders for visual organization. Include in PDF output for review distribution.
Test points are dedicated pads or loops on the PCB that provide access for probing, measurement, and automated testing. They must be identified on the schematic with clear designation (TP1, TP2, etc.), labeled with the signal they provide access to, and designed for the testing method (scope probe, bed-of-nails fixture, pogo pin, flying probe). Critical signals that need test points include: all power rails, clock signals, communication buses, reset, and any signal that cannot be accessed at a component pin.
Test points are not afterthoughts - they are design requirements that must be planned from the schematic stage.
Without test points: production testing requires probing tiny IC pins (risk of damage, slow, unreliable contact), debugging requires soldering wires to 0402 pads (time-consuming, can damage board), and automated in-circuit testing is impossible (no fixture access points). A board without test points costs 10x more to debug during development and cannot be efficiently tested in production. Test points cost essentially nothing (empty pad) but save hours of engineering time and enable high-volume automated testing.
Complete test point allocation:
POWER TEST POINTS: TP1: VIN (input voltage, before protection) TP2: VCC_5V (after input regulator) TP3: VCC_3V3 (main digital rail) TP4: VCC_1V8 (MCU core) TP5: GND (star ground reference point) SIGNAL TEST POINTS: TP6: HSE_CLK (8MHz crystal output for frequency verification) TP7: UART1_TX (debug console output) TP8: UART1_RX (debug console input) TP9: nSYS_RESET (verify reset timing with scope) TP10: SPI1_SCK (verify clock quality and frequency) PRODUCTION TEST POINTS: TP11-TP14: ADC calibration points (known voltage divider outputs) TP15: PGOOD signal (power sequencing verification) TP16: MCU GPIO_TEST_MODE (pull high to enter factory test mode) All test points: 1.5mm pad diameter, top side accessible, 2.54mm grid aligned. Included in BOM: Keystone 5000 (SMD test point, gold-plated).
No test points: Board has no dedicated test points. All signals accessible only at IC pins (0.5mm pitch QFP) or 0402 component pads. During prototype bring-up, engineer spends 30 minutes per measurement point soldering a wire to probe. Accidentally bridges two pins while soldering to UART for debug output - shorts VCC to GPIO, damages MCU. In production, ICT fixture cannot be built (no probe points). Alternative: flying probe testing takes 3 minutes per board instead of 5 seconds with fixture. Production cost increases $2/board for 10,000 boards = $20,000 over the product lifetime.
KiCad: Use "TestPoint" library symbol. Assign TP reference designators. Include in PCB with dedicated footprint (single pad). Verify in 3D that they don't conflict with enclosure.
Altium: Use Test Point Manager for automated testpoint assignment. Verify ICT grid alignment with DRC rules. Generate test point report for fixture design.
OrCAD: Place test point symbols from library. Assign properties indicating purpose and access requirements. Generate test point report for production test engineering.