Module 2.9 - SI Simulation & Validation
Signal Integrity Review: Simulation methodology, IBIS models, and measurement correlation
Signal Integrity Review: Simulation methodology, IBIS models, and measurement correlation
IBIS (Input/Output Buffer Information Specification) models are essential for signal integrity simulation. They provide I/V curves, timing data, and package parasitics without revealing proprietary transistor-level circuit details. Every IC with high-speed I/O should have an IBIS model available before design starts.
An IBIS model file (.ibs) contains:
[Component] - IC identification, pin count, package type
[Package Model] - Package parasitic R, L, C per pin (or .pkg file)
[Pin] - Pin mapping (pin number to buffer model name)
[Model] - I/O buffer electrical model for each unique buffer type:
- Model_type: Input, Output, I/O, Open_drain, etc.
- Vin: Input voltage range
- C_comp: Die capacitance
- [Pullup]/[Pulldown]: I/V curves (typ/min/max corners)
- [GND Clamp]/[POWER Clamp]: ESD clamp I/V curves
- [Ramp]: dV/dt rise and fall rates (typ/min/max)
- [Rising Waveform]/[Falling Waveform]: V(t) waveforms into specific loads
IBIS-AMI models (for SerDes):
- Algorithmic model for TX equalization (FIR filter)
- Algorithmic model for RX equalization (CTLE, DFE, CDR)
- Used with channel S-parameters for end-to-end link simulation
- Format: .ami parameter file + .dll/.so executable model
| Vendor | Location | Model Quality |
|---|---|---|
| Intel/Altera | intel.com IBIS downloads, or FPGA software (Quartus) | Excellent (includes AMI for SerDes) |
| AMD/Xilinx | xilinx.com IBIS models page, Vivado tool generation | Excellent (configurable per I/O standard) |
| TI | Product page "Design files" section | Good (most products covered) |
| NXP | nxp.com product page downloads | Good (i.MX, LPC, Kinetis) |
| Micron | micron.com "Models and Tools" section | Excellent (DDR models with package) |
| Samsung | semiconductor.samsung.com, or request via FAE | Good (DRAM, eMMC) |
| Microchip/Atmel | microchip.com product page | Variable (newer parts better) |
| STMicro | st.com product IBIS section | Good (STM32, SPC5 families) |
| Analog Devices | analog.com product page | Good (ADC, DAC, amplifiers) |
Complete model set for DDR4 design:
SoC (NXP i.MX8M Plus): IBIS model v6.1 with DDR4 I/O models, 3 corners, package .pkg file with per-pin R/L/C including mutual coupling. AMI model for DDR PHY equalization.
DRAM (Micron MT40A512M16): IBIS model v6.0 with POD12 output models, configurable ODT settings (RTT_NOM, RTT_WR, RTT_PARK), package model for FBGA.
Both models validated with ibischk5 - zero errors, zero warnings.
IBIS model for processor is version 3.2 (circa 2005) with only [Ramp] data (no waveform tables). The model lacks min/max corners - only typical is provided. Package model shows L=2.5nH for all pins (clearly a generic placeholder). Simulation with this model will not provide meaningful results for DDR4-3200 timing analysis where picosecond accuracy is needed.
Model version matters: IBIS versions below v5.0 lack support for power-aware modeling, on-die termination, and advanced package models. For DDR4/SerDes simulation, require IBIS v5.0+ or IBIS-AMI models.
Package variant: Ensure the IBIS model matches YOUR specific package (BGA, QFP, etc.). Pin assignments and package parasitics differ between packages of the same IC die.
Corner conditions: "Slow" corner (max Tco, weak drive) is not the same as "best case" for all metrics. For hold time analysis, you need the "fast" corner (min Tco, strong drive). Always simulate all corners.
Pre-layout simulation uses idealized transmission line models (before routing is complete) to establish design constraints: maximum trace lengths, required termination, and impedance targets. It answers "Can this topology work?" before committing to a physical layout.
What to simulate pre-layout:
1. Topology validation: point-to-point vs multi-drop vs fly-by
2. Termination strategy: series vs parallel vs on-die, resistor values
3. Maximum trace length (from timing budget)
4. Driver strength selection (for configurable I/O like FPGAs)
5. ODT value optimization (for DDR interfaces)
6. Impedance target verification (does 40 ohm or 50 ohm give better results?)
7. Crosstalk tolerance (how close can traces be for this data rate?)
What to NOT rely on from pre-layout:
- Exact eye diagram numbers (post-layout needed for real discontinuities)
- Via transition effects (topology model doesn't include via geometry)
- Connector effects (simplified models in pre-layout)
- Coupled multi-line effects (pre-layout uses isolated lines)
HyperLynx LineSim Pre-Layout Setup:
1. Create new LineSim schematic
2. Add IC model: File > Assign Models > select IBIS (.ibs file)
3. Select specific pin/buffer model for driver and receiver
4. Add transmission line: T-line element, set Zo=50 ohm (from stackup)
5. Set propagation delay: Td = estimated_length * Tpd_per_inch
e.g., for 3 inches of stripline: Td = 3 * 174 ps = 522 ps
6. Add termination: Series R near driver (value = Zo - Ro_driver)
7. Run Oscilloscope simulation: observe waveform at receiver
8. Check: Vih/Vil crossing, overshoot <110% Vdd, undershoot >-0.3V
9. Sweep: vary Td from 100 ps to 1500 ps to find maximum length
Key outputs:
- Maximum trace length for clean waveform
- Optimal termination resistor value
- Required driver strength setting
- Noise margin at receiver (voltage and timing)
Pre-layout simulation for 100 MHz QSPI interface:
Driver: STM32H7 (IBIS model, 3.3V, 25 ohm drive strength selected)
Trace: 50 ohm stripline, swept from 0.5 to 4 inches
Load: W25Q256 flash (IBIS model, Cin = 6 pF)
Termination: 22 ohm series at driver (Rs + Ro = 22 + 25 = 47 ohm, close to Zo)
Result: Clean waveform up to 3 inches (>500 mV eye opening at receiver). Degradation begins at 3.5 inches (300 mV eye). Max spec: 3 inches.
Constraint output: "QSPI net class: max length = 3000 mil, Zo = 50 ohm, series R = 22 ohm"
HyperLynx LineSim: Best for quick pre-layout exploration. Drag-and-drop topology builder with IBIS model library. Supports batch simulation with parameter sweeps.
Cadence Sigrity SystemSI: Schematic-based topology entry with IBIS/IBIS-AMI support. More complex setup but better for multi-net analysis.
Keysight ADS: Use "Signal Integrity" workspace with ideal T-line models. Powerful parameter sweeping and optimization engines.
Post-layout simulation uses the actual routed geometry extracted from the PCB layout. It includes real via structures, actual trace lengths and coupling, connector models, and manufacturing-representative stackup. Post-layout results should be the final sign-off for signal integrity.
| Aspect | Pre-Layout | Post-Layout |
|---|---|---|
| Trace model | Ideal T-line (uniform Zo, Td) | Extracted RLGC with discontinuities |
| Via effects | Not modeled or lumped LC | Full 3D extracted S-parameters |
| Crosstalk | Not included | Full multi-conductor coupling extracted |
| Connector | Simplified or S-parameter only | Full connector model in context |
| Package | IBIS [Package] lumped model | Package S-parameter model (if available) |
| Accuracy | +/- 20-30% for timing | +/- 5-10% for timing (correlates to measurement) |
| Purpose | Establish constraints, select topology | Final verification, sign-off, debug |
2.5D Extraction (Method of Moments / Boundary Element):
Tool: Cadence Sigrity PowerSI, Ansys SIwave
Accuracy: Good for traces and planes, approximate for 3D structures
Speed: Fast (minutes for full board)
Best for: Signal-plane interactions, PDN impedance, broadside coupling
3D Extraction (FEM / FDTD):
Tool: Ansys HFSS, CST Studio, Cadence Clarity 3D
Accuracy: Highest (full-wave, includes radiation and cavity effects)
Speed: Slow (hours for complex structures)
Best for: Via arrays, connectors, BGA breakout, package models
Hybrid approach (recommended):
Use 3D for critical structures (vias, connectors, BGA)
Use 2.5D for traces and plane coupling
Combine results in channel-level simulation (cascaded S-parameters)
Post-layout correlation for PCIe Gen4 channel:
Pre-layout prediction: IL = 11.2 dB at 8 GHz, RL < -15 dB
Post-layout extraction (Sigrity PowerSI): IL = 12.8 dB at 8 GHz, RL = -12.3 dB (worse at connector via)
Difference: 1.6 dB additional loss (from via stubs and connector discontinuity not in pre-layout model).
Action: Back-drill specification added for connector vias. Re-extraction shows IL = 11.9 dB. RL improved to -14.5 dB.
Final eye margin (with EQ): 45% eye width, 22 mV eye height at BER=1e-12. Specification: 30% width minimum. PASS.
Eye mask compliance is the definitive pass/fail criterion for high-speed digital interfaces. The eye diagram must be clear of the specification mask at the target BER (typically 1e-12 or 1e-15). Both simulated and measured eyes must comply.
Eye mask is typically defined as a hexagonal or diamond-shaped keep-out zone:
___________
/ \ <-- Upper mask boundary
/ \
/ \
_____/ \_____ <-- 0-crossing boundaries
\ /
\ /
\ /
\___________/ <-- Lower mask boundary
Key parameters:
- Eye Width: horizontal opening at 0-crossing (in UI or time)
- Eye Height: vertical opening at sampling point (in mV)
- Mask margin: extra clearance beyond mask boundary
For compliance testing:
BER = number of mask violations / total number of bits
Target: BER < 1e-12 (no violations in 10^12 bit samples)
Statistical eye: calculates BER at every point from noise distribution
Time-domain eye: overlay of N bits (limited statistical confidence)
Measurement: oscilloscope with mask test (limited to ~10^9 bits practical)
Simulation-based compliance:
1. Extract channel S-parameters (post-layout)
2. Configure IBIS-AMI TX model (with equalization coefficients)
3. Configure IBIS-AMI RX model (CTLE + DFE settings)
4. Run statistical eye (preferred) or time-domain with PRBS-31 pattern
5. Apply specification eye mask
6. Report: pass/fail, eye height margin, eye width margin, bathtub curves
Measurement-based compliance (lab verification):
1. Apply PRBS-31 pattern from TX (using pattern generator or loopback mode)
2. Measure with real-time oscilloscope or sampling oscilloscope
3. Apply reference equalizer (defined in spec) to measured waveform
4. Overlay mask and count violations
5. Report: measured eye parameters, jitter decomposition, BER bathtub
Measurement point matters: USB, PCIe, and Ethernet all define different "compliance points" (where the eye is measured). PCIe Gen4 defines the eye at the RX input AFTER the RX package. USB defines it at the connector. Measuring at the wrong point invalidates the result.
Equalization settings for compliance: The spec defines which EQ is applied for compliance testing. For PCIe Gen4, the "reference equalizer" is a specific CTLE + DFE defined in the specification. Using different EQ settings gives different (non-compliant) eye openings.
Time Domain Reflectometry (TDR) provides a spatial map of impedance along a signal path. It reveals the location and magnitude of every impedance discontinuity, making it invaluable for debug and production verification.
TDR resolution (minimum feature size detectable):
Spatial resolution = (rise_time * v_prop) / 2
For 20 ps rise time in FR4: resolution = (20e-12 * 1.5e8) / 2 = 1.5 mm (59 mil)
For 35 ps rise time: resolution = 2.6 mm (102 mil)
Impedance from TDR reflection:
Zo_DUT = Zo_system * (1 + rho) / (1 - rho)
Where: rho = V_reflected / V_incident (measured from TDR waveform)
Zo_system = 50 ohm (instrument reference impedance)
Time-to-distance conversion:
Distance = (time * v_prop) / 2 (divide by 2 because TDR measures round-trip)
In FR4 stripline: v_prop = 1/(Tpd) = 1/(174 ps/inch) = 5.75 inch/ns
So: distance (inches) = time (ns) * 5.75 / 2 = time * 2.87
TDR MEASUREMENT PLAN
Project: [Board Name] Rev: [A] Date: [YYYY-MM-DD]
Equipment:
Instrument: Tektronix DSA8300 with 80E10B TDR module (9 ps rise time)
Probes: P8018 TDR probe tips (GS or GSG configuration)
Calibration: SOL cal with CS-5 calibration substrate
Measurements Required:
# Net Name Location Expected Zo Tolerance Notes
1 DDR4_DQ0 Test coupon 1 40 ohm +/-10% Stripline L3
2 DDR4_DQS0_P Test coupon 1 80 ohm diff +/-10% Diff pair L3
3 PCIE_TX0_P Test coupon 2 85 ohm diff +/-10% Stripline L6
4 USB3_TX_P Board J2-pin1 85 ohm diff +/-10% Through connector
5 ETH_MDI0_P Board J5-pin1 100 ohm diff +/-10% To connector
Procedure:
1. Calibrate TDR at probe tips using SOL standards
2. Connect to test point (coupon launch pad or board trace access)
3. Set time window to capture full trace length + 20% margin
4. Record impedance profile (save waveform data)
5. Identify all discontinuities and their physical locations
6. Compare measured impedance to specification limits
7. Document results with screenshots and impedance values
Acceptance Criteria:
- Average impedance within +/-10% of target (or per interface spec)
- No single-point excursion > +/-15% of target (spike limit)
- Via transitions: impedance recovers within 50 ps of entering via
Tektronix DSA8300: Industry standard for high-bandwidth TDR. The 80E10B module provides 9 ps rise time (ideal for PCIe Gen4+ and DDR4 measurements). Supports differential TDR with two channels.
Keysight N1930B: Physical Layer Test System combines TDR, S-parameters, and eye diagram in one instrument. Automated fixture de-embedding for removing probe effects.
Picotest J2151A: Budget-friendly TDR with 40 ps rise time. Adequate for DDR3, USB2, and low-speed controlled impedance. Not sufficient for PCIe Gen3+.
The ultimate validation of the SI design process is demonstrating that simulations accurately predict measured results. Good correlation (within 10-15%) builds confidence in the simulation methodology and enables future designs to rely on simulation for sign-off.
Correlation metrics:
1. Impedance: simulated vs measured TDR profile (target: within 5%)
2. Insertion loss: simulated vs measured S21 (target: within 1 dB)
3. Return loss: simulated vs measured S11 (target: within 3 dB)
4. Propagation delay: simulated vs measured (target: within 5%)
5. Eye diagram: simulated vs measured eye height/width (target: within 20%)
Common causes of simulation-measurement mismatch:
- Dk/Df values in simulation don't match actual material at frequency
- Copper roughness not modeled (or incorrect roughness parameters)
- Manufacturing variation (etch under/over, dielectric thickness shift)
- Measurement fixture not de-embedded properly
- Probe loading effect (especially for single-ended high-Z probes)
- Model simplifications (2.5D vs 3D, lumped vs distributed elements)
Acceptable correlation targets:
Impedance: simulated 50 ohm, measured 48-52 ohm (within 4%)
Loss at 5 GHz: simulated 8 dB, measured 7.2-8.8 dB (within 10%)
Delay: simulated 500 ps, measured 475-525 ps (within 5%)
Eye height: simulated 30 mV, measured 25-35 mV (within 20%)
SI CORRELATION REPORT
=====================
Board: ACME-SERVER-v3 Fab: TTM Technologies Lot: 2024-0042
Date: 2024-03-15 Engineer: [Name]
STACKUP CORRELATION:
Layer Nominal Dk Simulated Dk Measured Dk (coupon) Delta
L1-L2 4.2 4.2 4.15 -1.2%
L3 core 4.3 4.3 4.28 -0.5%
IMPEDANCE CORRELATION:
Structure Target Simulated Measured (TDR) Delta
50 ohm ustrip 50 50.2 48.5 -3.4%
85 ohm diff 85 85.3 83.1 -2.6%
40 ohm strip 40 40.1 39.2 -2.2%
INSERTION LOSS CORRELATION (at Nyquist):
Channel Simulated Measured (VNA) Delta
PCIe Lane 0 12.3 dB 13.1 dB +0.8 dB (roughness underestimated)
USB3 TX 8.7 dB 9.2 dB +0.5 dB
EYE DIAGRAM CORRELATION:
Interface Sim Eye Height Meas Eye Height Delta
PCIe Gen4 Lane 0 28 mV 24 mV -14% (acceptable)
USB3 Gen2 68 mV 62 mV -9%
ACTIONS:
1. Update Dk from 4.2 to 4.15 for outer layer (improves impedance correlation)
2. Increase copper roughness Rz from 3 um to 4.5 um (improves loss correlation)
3. Archive updated material model for future designs with this fab
Iterative correlation achievement:
First design: 15% impedance error, 2.5 dB loss error (using generic FR4 models).
After material characterization: 5% impedance error, 0.8 dB loss error.
After roughness model update: 3% impedance error, 0.5 dB loss error.
Third design with same fab/material: 2% impedance, 0.3 dB loss - excellent correlation.
Now confident enough to sign-off PCIe Gen5 design based on simulation alone (first article confirms).
Simulation predicts PCIe Gen4 channel has 25 dB IL at 8 GHz (within 28 dB spec). No correlation ever performed with this fabricator. Actual measured IL = 31 dB (exceeds spec by 3 dB). Root cause: fab uses rougher copper treatment than assumed (Rz = 6 um vs assumed 3 um). The 3 dB error was due to uncharacterized copper roughness. Link fails at Gen4 speed, works only at Gen3. Requires board respin with smoother copper (VLP treatment) - 6 week delay.
VNA Measurement: Keysight E5071C (up to 20 GHz) or R&S ZNB (up to 40 GHz) with calibrated test fixture. Use electronic calibration (ECal) for speed and repeatability. Capture S2P/S4P files for direct comparison with simulation.
Comparison Tools: Keysight ADS "Compare S-params" utility. Cadence Sigrity "Correlation Manager." Or simply overlay Touchstone files in any S-parameter viewer (free tools: S-Param Viewer by Copper Mountain, RFSim99).
Material Characterization: Keysight N1500A Materials Measurement Suite with split-post dielectric resonator for Dk/Df at specific frequencies. Or use Bereskin method (test trace pair, extract Dk/Df from measured IL and phase).