Module 2.4 - Timing & Length Matching

Checkpoint 2.4.1: Setup/Hold Time Margins Critical

Setup time (Tsu) is the minimum time data must be stable BEFORE the clock edge. Hold time (Th) is the minimum time data must remain stable AFTER the clock edge. Violating either causes metastability and data corruption.

Timing Analysis Fundamentals

Interface Timing Specifications

Worked Example: RGMII Timing

RGMII 1000BASE-T (125 MHz, DDR = data at both edges):
  T_period = 8 ns (1/125 MHz), effective window per edge = 4 ns (DDR)

PHY (KSZ9031) to MAC (i.MX8M):
  T_co_max (PHY) = 2.0 ns
  T_co_min (PHY) = 0.5 ns
  T_su (MAC) = 1.0 ns
  T_hold (MAC) = 1.0 ns

RGMII spec requires data centered on clock at receiver:
  Required data-to-clock skew at receiver: 1.5 to 2.5 ns

PCB contribution:
  Trace length CLK: 2.0 inches, Delay: 2.0 * 170 ps/in = 340 ps
  Trace length DATA: 2.0 inches, Delay: 340 ps
  Skew if matched: 0 ps

But RGMII needs 1.75 ns internal delay (added by PHY in RGMII mode):
  PHY internal TX_CLK delay = 2.0 ns (enabled via register)

Setup margin = 4.0 - 2.0 - 0.0 (matched) - 1.0 - 0.1 (jitter) = 0.9 ns PASS
Hold margin = 0.5 + 0.0 - 1.0 - 0.1 = -0.6 ns FAIL!

Solution: Enable PHY internal delay (adds 2 ns to clock path):
  Effective Tco_min with delay = 0.5 + 2.0 = 2.5 ns
  Hold margin = 2.5 + 0.0 - 1.0 - 0.1 = 1.4 ns PASS
  Setup margin = 4.0 - (2.0+2.0) - 0.0 - 1.0 - 0.1 = -1.1 ns FAIL!

Correct approach: Use only TX delay (2 ns), not both:
  Setup margin = 4.0 - 2.0 - 0.0 - 1.0 - 0.1 = 0.9 ns (data arrives 0.9 ns before clock)
  With TX delay on: clock arrives 2.0 ns AFTER data change
  Effective setup seen by receiver = 2.0 ns > 1.0 ns PASS
  Effective hold seen by receiver = 4.0 - 2.0 = 2.0 ns > 1.0 ns PASS
            

Step-by-Step Verification

1. Extract Tco, Tsu, Th from transmitter and receiver datasheets for each interface.
2. Determine clock architecture: system-synchronous vs source-synchronous vs embedded clock.
3. Calculate PCB flight time for clock and data using propagation delay (typically 140-170 ps/inch).
4. Calculate setup and hold margins using the formulas above.
5. Include jitter budget: typically 5-10% of the data window for deterministic + random jitter.
6. Verify BOTH setup AND hold margins are positive with adequate guardband (>10% of window).

Checkpoint 2.4.2: Flight Time Calculations Critical

Flight time is the propagation delay from driver output pin to receiver input pin, including PCB trace delay, via delays, connector delays, and any series component delays.

Propagation Delay Formulas

Propagation Delay Reference Table

Flight Time Calculation Example

Signal: DDR4 DQ[0] from SoC (U1 pin A5) to DRAM (U3 pin B7)

Path breakdown:
  Segment 1: BGA fanout on L1 (microstrip)      = 0.3 inches * 139 ps/in = 42 ps
  Via 1: L1 to L3 transition                     = 12 ps
  Segment 2: Main route on L3 (stripline)        = 1.8 inches * 174 ps/in = 313 ps
  Via 2: L3 to L1 transition                     = 12 ps
  Segment 3: Fanout to DRAM on L1 (microstrip)   = 0.2 inches * 139 ps/in = 28 ps

Total flight time: 42 + 12 + 313 + 12 + 28 = 407 ps

For length matching, the EQUIVALENT length (normalized to one Tpd):
  If normalizing to stripline: 407 ps / 174 ps/in = 2.34 equivalent inches
  If normalizing to microstrip: 407 ps / 139 ps/in = 2.93 equivalent inches

Most EDA tools match physical length, not delay!
Correction: 0.3" microstrip = 0.3 * (139/174) = 0.24" stripline equivalent
            

Step-by-Step Verification

1. Extract the complete signal path from schematic and layout (all segments, vias, connectors).
2. Determine the propagation delay for each segment based on layer type and dielectric.
3. Sum all segment delays to get total flight time.
4. If signals traverse multiple layer types, calculate delay-equalized length (not just physical length).
5. Document flight times for all critical nets in a timing spreadsheet.
6. Compare calculated flight times against timing budget requirements.

Checkpoint 2.4.3: Length Matching Tolerance Per Interface Critical

Length matching ensures that signals within a bus arrive at the receiver within a specified time window. The tolerance depends on the interface speed and timing margins.

Length Matching Requirements

Length Matching Methods

Method 1: Serpentine/Accordion Tuning
  - Add meanders (serpentine routing) to shorter traces
  - Minimum serpentine amplitude: 3x trace width (to avoid self-coupling)
  - Minimum serpentine spacing: 3x trace width (3W rule within meanders)
  - Maximum single-segment meander: keep under 1/3 of total meander
  - Place meanders near the SOURCE end (not near receiver)

Method 2: Sawtooth/Trombone Tuning
  - Route in sawtooth pattern for differential pairs
  - Maintains constant pair spacing (critical for impedance)
  - Preferred for differential signals over serpentine

Method 3: Trace routing adjustment
  - Lengthen shorter traces through natural routing path variation
  - Most elegant solution - no meanders visible
  - Requires careful planning during placement

Key Rule: Match DELAY, not just LENGTH when mixing layers!
  1 inch on microstrip (Er_eff=3.2) = 139 ps
  1 inch on stripline (Er=4.2) = 174 ps
  To match delay: 1" stripline = 1.25" microstrip equivalent
            

Step-by-Step Verification

1. Define length matching groups in EDA constraint system (e.g., DDR4_BYTE0_DQ group).
2. Set matching tolerance per group from the interface specification (see table above).
3. Route all signals in a group on the same layer type where possible (avoids delay mismatch).
4. If layer changes required, use delay-based matching (not physical length).
5. Add length tuning (serpentine) to shorter traces to meet tolerance.
6. Run DRC length matching report - verify all groups pass within tolerance.
7. Review serpentine geometry: minimum 3W spacing between meander segments.

Checkpoint 2.4.4: Skew Budget Allocation Major

Total skew budget must account for all contributors: IC package, PCB routing, connector, manufacturing variation, and temperature effects. The PCB routing budget is only one component.

Skew Budget Breakdown

Step-by-Step Budget Creation

1. Obtain total allowable skew from interface specification (e.g., JEDEC for DDR, PCI-SIG for PCIe).
2. Extract package skew data from IBIS models or IC vendor reference design documentation.
3. Allocate remaining budget to PCB routing (typically 40-60% of total after IC package allocation).
4. Convert PCB timing budget to physical length tolerance using layer-specific Tpd.
5. Include manufacturing variation estimate (typically +/- 5% of trace length for etch variation).
6. Verify RSS total is within specification with positive margin.

Checkpoint 2.4.5: Clock-to-Data Timing Critical

The relationship between clock and data paths determines where in the data eye the clock captures data. For source-synchronous interfaces, the clock must sample at the center of the data valid window.

Clock-Data Relationship by Architecture

1. SOURCE-SYNCHRONOUS (clock travels with data):
   Examples: DDR SDRAM, RGMII, source-synchronous LVDS
   Goal: Clock EDGE aligned with data CENTER at receiver
   Method: Match clock and data trace lengths (within spec tolerance)

   DDR4 approach: DQS strobe is edge-aligned with DQ at transmitter.
   At receiver, DQS is delayed by 90 degrees (via DLL) to sample at data center.
   PCB task: Match DQ to DQS within byte lane (+/- 10 mil)

2. SYSTEM-SYNCHRONOUS (common clock, data and clock from same source):
   Examples: SPI, I2C, SDIO, legacy parallel buses
   Goal: Data valid at receiver when clock edge arrives
   Method: Ensure Tco + Tflight < Tperiod - Tsu

3. EMBEDDED CLOCK (clock recovered from data):
   Examples: PCIe, USB 3.x, SATA, Ethernet SerDes
   Goal: No clock routing needed! Clock is in the data stream.
   Method: Maintain channel quality (loss, jitter) for CDR to lock
   PCB task: Impedance control, minimize loss, AC coupling caps

4. FORWARDED CLOCK (separate clock, but source-synchronous):
   Examples: RGMII TX_CLK, DDR CA clock
   Goal: Clock arrives at correct phase relative to data
   Method: Specific length relationship (may need clock longer/shorter)
            

RGMII Clock-Data Timing Example

Step-by-Step Verification

1. Identify the clock architecture for each interface (source-sync, system-sync, embedded, forwarded).
2. For source-synchronous: determine the required phase relationship at the receiver.
3. Check if internal delays are available in the IC (register settings, DLL, PLL).
4. Calculate required PCB trace length relationship between clock and data.
5. Implement length matching rules in EDA constraints.
6. After routing, verify clock-to-data delay meets specification at receiver pins.

Checkpoint 2.4.6: Group Delay Variation Minor

Group delay variation (also called delay distortion) occurs when different frequency components of a signal travel at different speeds. This causes pulse distortion and reduces timing margins, especially for broadband signals.

Group Delay Fundamentals

Step-by-Step Verification

1. For SerDes channels >10 Gbps, extract S-parameters from post-layout simulation.
2. Plot group delay vs frequency: tau_g(f) = -d(angle(S21))/d(f) / (2*pi).
3. Identify any sharp peaks (indicating resonances from via stubs or cavity modes).
4. Verify group delay variation is within spec across the signal bandwidth (DC to Nyquist).
5. If excessive variation found, identify root cause (usually via stubs) and mitigate (back-drill, shorter stubs).
6. For critical channels, include group delay specification in fabrication requirements.