Module 3.8 - PI Simulation & Measurement

Checkpoint 1: DC IR-Drop Simulation Performed Critical

DC IR-drop analysis determines the static voltage loss from the VRM output to each IC power pin due to the finite resistance of copper traces, planes, and vias. For low-voltage rails (0.85V, 1.0V), even small IR drops (10-20mV) represent significant percentage losses that reduce voltage margin.

IR-Drop Physics

Sigrity PowerDC Workflow

1. Import Design: File > Import > Select ODB++ or Allegro .brd file. Verify all layers imported correctly with proper copper weights.
2. Net Assignment: Setup > Nets > Select power net (e.g., VCCINT) and ground net (GND). Verify complete connectivity (no floating islands).
3. Assign Current Sources: Setup > Sources > Place voltage source at VRM output pad. Set voltage to nominal output value.
4. Assign Current Sinks: Setup > Sinks > Place current sinks at each IC power pin. Set current values from power budget spreadsheet (per-pin allocation).
5. Copper Weight Setup: Setup > Stackup > Verify copper thickness for each layer matches fabrication stackup drawing.
6. Temperature: Setup > Temperature > Set ambient and initial copper temperature (25C default, or max operating ambient).
7. Solve: Analysis > DC > Run. Wait for convergence (typically 30s to 5 minutes depending on complexity).
8. Review Results: Results > Voltage Map (shows voltage distribution across plane). Results > Current Density Map (shows hot spots).

Interpreting DC IR-Drop Results

Checkpoint 2: AC Impedance Simulation Done Critical

AC impedance simulation computes the PDN impedance as seen from the IC power pins across the frequency range (typically 100Hz to 10GHz). This is the definitive check that the complete PDN (VRM + caps + planes + vias) meets the target impedance at all frequencies.

Simulation Setup Parameters

Sigrity PowerSI AC Impedance Workflow

1. Import and Setup: Same as DC analysis - import layout, assign nets, verify stackup.
2. Place Observation Ports: Place Z-parameter ports at IC power pin locations. For BGA ICs, place ports at representative pins (corners, center, near sensitive blocks).
3. VRM Model: Replace VRM with equivalent circuit: R_out in series with L_out, parallel with VRM output capacitor bank. Or import VRM S-parameter model if available.
4. Component Library: Setup > Component Models > Map each decoupling cap designator to its S2P model. Bulk caps: use series RLC. MLCC: use vendor S2P.
5. Solver Settings: Set frequency range (100Hz-10GHz), enable "Accurate" mode for plane meshing, set mesh size < lambda/20 at max frequency.
6. Run Analysis: Typical runtime: 10-60 minutes depending on board complexity and frequency range.
7. Post-process: Plot Z11 (self-impedance at each IC port). Overlay Z_target line. Identify any frequency where Z > Z_target.
8. Optimize: If violations found: modify cap values, add caps, change placement, adjust VRM. Re-run to verify fix.

Key Results to Extract

• Z vs Frequency plot: Primary deliverable. Must be below Z_target line at all frequencies.
• Peak impedance value and frequency: Identifies worst-case point and which PDN element transition causes it.
• Resonance frequencies: Anti-resonance peaks that may need damping.
• Self vs Transfer impedance: Z11 (self) at each port, Z12/Z21 (coupling between ports) for noise coupling analysis.
• Phase information: Phase of Z indicates whether PDN is capacitive (negative phase) or inductive (positive phase) at each frequency.

Checkpoint 3: Voltage Ripple Simulation Validated Major

Time-domain voltage ripple simulation predicts the actual voltage waveform at IC power pins under realistic operating conditions. Unlike impedance analysis (which is a frequency-domain assessment), ripple simulation shows the combined effect of VRM switching, load current transients, and PDN filtering in the time domain.

Ripple Sources and Their Contribution

Simulation Approach

1. Define excitation: Create realistic current profile from IC switching activity model (toggle rate, clock frequency, worst-case pattern).
2. VRM model: Include full switching model of regulator (or use simplified model with output impedance + ripple current source).
3. Time step: Set simulation time step < 1/(10 * f_max). For 1GHz signals: dt < 100ps. For VRM ripple only: dt < 100ns.
4. Simulation duration: Run for at least 10-20 switching cycles of the lowest frequency component to establish steady state.
5. Monitor points: Observe voltage at IC power pins, VRM output, and intermediate points of interest.
6. Analysis: Measure peak-to-peak ripple, RMS ripple, and compare against IC specification.

Checkpoint 4: Power-Up Transient Simulated Major

Power-up transient simulation verifies the voltage ramp behavior of each rail during startup, including interactions between sequenced rails, inrush current, VRM behavior during soft-start, and any voltage overshoots or non-monotonic behavior. This simulation catches sequencing violations that DC and AC analyses cannot reveal.

What to Simulate

• Individual rail ramp profiles (voltage vs time from 0V to regulation)
• Multi-rail sequencing timing (verify no rail violates sequence order)
• Inrush current profile (verify no fuse trip or input supply collapse)
• Monotonic rise verification (no dips during ramp)
• Interaction between rails (one rail enabling causes glitch on another)
• Pre-bias behavior (what happens if output has residual voltage from prior cycle)

Simulation Setup in SPICE

* Power-up transient simulation - FPGA board
* TPS62130 buck converter model (simplified)

.tran 0.1us 20ms  ; 20ms total, 100ns time step

* Input supply (12V with soft-start behavior)
V_input input_12v GND PWL(0 0 1ms 12 20ms 12)

* VRM 1: VCCINT (0.85V) - enables at t=1ms
X_vrm1 input_12v vccint GND en1 TPS62130
+ VOUT=0.85 FSW=2.5MEG L=2.2U COUT=44U SS=2ms
V_en1 en1 GND PWL(0 0 1ms 0 1.001ms 3.3)

* VRM 2: VCCAUX (1.8V) - enables when VCCINT PG asserts (~3ms)
X_vrm2 input_12v vccaux GND en2 TPS62130
+ VOUT=1.8 FSW=2.5MEG L=4.7U COUT=22U SS=2ms
V_en2 en2 GND PWL(0 0 3.5ms 0 3.501ms 3.3)

* VRM 3: VCCIO (3.3V) - enables when VCCAUX PG asserts (~5.5ms)
X_vrm3 input_12v vccio GND en3 TPS62130
+ VOUT=3.3 FSW=2.5MEG L=6.8U COUT=22U SS=3ms
V_en3 en3 GND PWL(0 0 6ms 0 6.001ms 3.3)

* Load models (ramping as IC initializes)
I_load1 vccint GND PWL(0 0 5ms 0 10ms 5 20ms 15)
I_load2 vccaux GND PWL(0 0 7ms 0 12ms 1 20ms 2)
I_load3 vccio GND PWL(0 0 9ms 0 14ms 0.5 20ms 1)

.probe V(vccint) V(vccaux) V(vccio) I(V_input)
            

Key Things to Verify in Results

1. Each rail reaches regulation voltage within specified time (typically < 20ms total).
2. Sequence order is correct: VCCINT before VCCAUX before VCCIO (for this FPGA).
3. No rail exceeds its maximum voltage at any time during startup.
4. Monotonic rise on all rails (no dips exceeding 50mV).
5. Input current never exceeds supply capability or fuse rating.
6. Ramp rate within IC specification for each rail.
7. Power-good timing provides adequate margin for next stage enable.

Checkpoint 5: Measurement Plan Defined Major

A measurement plan documents what will be measured, where, with what equipment, and what pass/fail criteria apply. Having a plan before board fabrication ensures test points are included in the layout, appropriate probe access is available, and the validation team knows exactly what to verify on first power-up.

Essential PI Measurements

Test Point Requirements for PI Validation

Measurement Plan Template

POWER INTEGRITY MEASUREMENT PLAN
Board: [Project Name] Rev [A]
Date: [Date]
Engineer: [Name]

1. FIRST POWER-UP (No-load)
   [ ] Input current (should be < quiescent spec)
   [ ] All rail voltages (DMM, 4-wire if possible)
   [ ] Power-up sequence (4-ch scope, all rails)
   [ ] Thermal scan (IR camera, 5 minutes at no-load)

2. STEADY-STATE (Full load)
   [ ] All rail voltages under load
   [ ] Output ripple (scope, 20MHz BW limit + full BW)
   [ ] Efficiency measurement (Pin vs Pout)
   [ ] Thermal scan at steady-state (30min runtime)

3. TRANSIENT TESTING
   [ ] Load step response (50% step, each rail)
   [ ] Full-load to no-load overshoot
   [ ] Power cycling (100x rapid on/off)

4. IMPEDANCE MEASUREMENT (if VNA available)
   [ ] PDN impedance vs frequency (2-port shunt-through)
   [ ] Compare to simulation results

5. ENVIRONMENTAL
   [ ] Repeat critical tests at temperature extremes
   [ ] Repeat at minimum/maximum input voltage
            

Checkpoint 6: Simulation-Measurement Correlation Minor

Correlation between pre-layout simulation predictions and post-fabrication measurements validates the simulation methodology and builds confidence for future designs. Good correlation (within 20-30%) confirms the models and assumptions are correct. Poor correlation flags issues with either the simulation setup or the measurement technique.

Correlation Methodology

1. Measure PDN impedance: Use VNA with 2-port shunt-through method at the same location where simulation port was placed.
2. Import measurement data: Load S2P measurement file into simulation tool.
3. Overlay plots: Plot simulated Z vs measured Z on same axes, same frequency range.
4. Quantify differences: Calculate error at key frequencies (resonances, anti-resonances, flat regions).
5. Identify discrepancies: Systematic shifts indicate model issues. Random differences indicate measurement noise.
6. Refine model: Adjust parameters to match measurement (this calibrated model is used for future designs on same stackup).
7. Document: Record correlation quality and any model adjustments for design reuse.

2-Port Shunt-Through Impedance Measurement

Expected Correlation Quality

Common Correlation Issues and Fixes