Tutorial 5.10: Fabrication Outputs

Introduction to Fabrication Output Generation

The fabrication output package is the final deliverable that translates your PCB design into manufacturing instructions. Even a perfectly designed board will be manufactured incorrectly if the output files are wrong, incomplete, or ambiguous. This tutorial covers the complete output generation workflow, file verification procedures, and common errors that cause manufacturing problems.

Complete Output File Set

Checkpoint: Gerber RS-274X Generated for All Layers

Required Gerber File List (8-Layer Board Example)

Gerber Generation Settings

Recommended Gerber output settings:
===================================
Format:         RS-274X (embedded apertures) or Gerber X2
Coordinate:     Metric (mm) preferred for modern fabs; imperial (inch) also accepted
Resolution:     4.6 (4 integer, 6 decimal in metric = 0.001um precision)
                or 2.5 (2 integer, 5 decimal in imperial = 0.00001 inch)
Units:          Millimeters (preferred) or Inches
Zero suppress:  Leading zero suppression (most common)
Mirroring:      NEVER mirror any layer in output (fab does this for bottom layers)
Polarity:       Positive (dark is copper) for signal layers
                Negative (clear is opening) sometimes used for plane layers
                (Check fabricator preference - most prefer all positive)
            

Checkpoint: Excellon Drill File with Correct Format

Drill File Requirements

Drill File Verification

1. Open in Gerber viewer: Load drill file alongside copper Gerber. Verify drill hits align with pads
2. Check tool table: All drill sizes match design (no extra/missing tools)
3. Verify unit consistency: Drill file units match Gerber file units
4. Count hits: Total drill count should match the design's drill summary report
5. Check for duplicates: No drill hit at the same location twice (causes over-drilling)
6. Verify PTH/NPTH separation: Mounting holes must be in NPTH file, not PTH
7. Slot definition: Routed slots defined as slot (G85 command) not as multiple drill hits

Common Drill File Format

Excellon Drill File Header Example:
M48                          ; Header start
METRIC,LZ                    ; Metric units, Leading Zero suppression
T1C0.200                     ; Tool 1: 0.200mm diameter
T2C0.300                     ; Tool 2: 0.300mm diameter
T3C0.400                     ; Tool 3: 0.400mm diameter
T4C1.000                     ; Tool 4: 1.000mm diameter
T5C3.200                     ; Tool 5: 3.200mm (mounting hole)
%                            ; End of header
T1                           ; Select tool 1
X015000Y020000               ; Drill at X=15.000, Y=20.000
X015500Y020000               ; Drill at X=15.500, Y=20.000
...
T2                           ; Select tool 2
X010000Y010000
...
M30                          ; End of file
            

Checkpoint: Pick-and-Place File Coordinates Verified

Pick-and-Place File Format

Standard CSV Format:
RefDes, PosX(mm), PosY(mm), Rotation(deg), Side, Value, Package
C1, 25.400, 12.700, 0, Top, 100nF, 0402
C2, 25.400, 14.200, 180, Top, 100nF, 0402
U1, 50.000, 40.000, 0, Top, STM32F4, LQFP-64
U2, 30.000, 25.000, 90, Bottom, LM3671, SOT-23-5
R1, 22.000, 10.000, 270, Top, 10K, 0402
...

Required columns:
  - Reference Designator (unique identifier)
  - X Position (component center/origin, in mm or mils)
  - Y Position (component center/origin, in mm or mils)
  - Rotation (degrees, CCW from positive X axis)
  - Side (Top or Bottom)

Optional but recommended:
  - Component Value
  - Package/Footprint name
  - Part Number / MPN
            

Verification Procedure

1. Open pick-and-place file in spreadsheet (verify all columns parse correctly)
2. Count components: total should match BOM component count (SMD only)
3. Verify Top/Bottom assignment matches actual board side
4. Overlay centroid coordinates on Gerber copper layer in viewer
5. Spot-check 5+ components per side:
   • Check X,Y of IC center aligns with footprint center
   • Check rotation is correct (pin 1 in right position)
   • Verify asymmetric components (connectors, ICs) have correct orientation
6. Check for missing components (compare ref-des list to BOM)
7. Verify origin/datum point matches assembly house requirement (usually board corner or fiducial)

Checkpoint: IPC-D-356 Netlist for Testing

IPC-D-356 Netlist Purpose

The IPC-D-356 netlist file tells the bare-board electrical tester which points should be connected (net assignments) and which should be isolated. The tester verifies:

• Continuity: All points in a net are electrically connected (no open circuits)
• Isolation: Points on different nets are NOT connected (no short circuits)
• Test coverage: Percentage of nets that can be accessed for testing

IPC-D-356 File Format

IPC-D-356 Format Example:
P  JOBNAME    UNITS=MM
999
327VCC          A01X+015000Y+020000X0060Y0060R000 S1
327VCC          A02X+015500Y+020000X0050Y0050R000 S1
327GND          A01X+010000Y+010000X0060Y0060R000 S1
327GND          A02X+010500Y+010000X0050Y0050R000 S1
327NET1         A01X+020000Y+030000X0040Y0040R000 S1
327NET1         A02X+025000Y+030000X0040Y0040R000 S1
999

Each record (327 type) contains:
  - Net name
  - Access point designation
  - X,Y coordinates of test point
  - Pad dimensions
  - Rotation
  - Side (S1=top, S2=bottom)
            

Verification Steps

1. Generate IPC-D-356 file from EDA tool
2. Verify net count in file matches design net count
3. Check that all nets have at least 2 test points (otherwise untestable)
4. Verify single-pin nets are properly flagged
5. Calculate test coverage: (testable nets / total nets) x 100%
6. Target: 99%+ coverage for production boards; 95%+ minimum

Checkpoint: Fabrication Drawing with Notes

Required Fabrication Drawing Contents

Fabrication Drawing Checklist:
================================

GENERAL INFORMATION:
[ ] Board name and part number
[ ] Drawing revision and date
[ ] Board dimensions (overall L x W x T)
[ ] Number of layers
[ ] IPC Class (Class 2 or Class 3)
[ ] Surface finish (HASL, ENIG, OSP, Immersion Silver, etc.)
[ ] Solder mask color (both sides)
[ ] Silkscreen color (both sides)

MATERIAL SPECIFICATION:
[ ] Base material (FR-4, High-Tg, Rogers, etc.)
[ ] Specific laminate (e.g., "Isola 370HR" or "TU-872")
[ ] Tg requirement (e.g., "Tg >= 170C by DSC")
[ ] UL flame rating (UL94 V-0 typical)
[ ] Dk/Df values at operating frequency (for controlled impedance)

COPPER AND STACKUP:
[ ] Stackup cross-section diagram with all layer labels
[ ] Copper weight per layer (oz)
[ ] Dielectric thickness between layers (mil or mm)
[ ] Core and prepreg identification (style numbers)
[ ] Overall board thickness with tolerance (e.g., 1.6mm +/- 10%)

IMPEDANCE CONTROL:
[ ] Impedance table: Layer, Type (SE/Diff), Target, Tolerance, Width, Spacing
[ ] Impedance test coupon requirement
[ ] TDR measurement report required (yes/no)

DRILL INFORMATION:
[ ] Drill table (all tool sizes, plated/non-plated, count)
[ ] Minimum and maximum drill sizes
[ ] Aspect ratio of smallest via
[ ] Blind/buried via specification (if used)
[ ] Back-drill specification (if used)
[ ] Slot routing specification

SPECIAL PROCESSES:
[ ] Via fill type (if via-in-pad used) per IPC-4761
[ ] Edge plating (if required)
[ ] Selective gold plating (e.g., connector fingers)
[ ] Carbon printing (for contacts/switches)
[ ] Peelable mask (for selective soldering areas)
[ ] Countersink/counterbore details
            

Surface Finish Selection Guide

Checkpoint: Stackup Specification Document

Stackup Document Content

STACKUP SPECIFICATION
=====================
Project: [Name]  |  Rev: [A]  |  Date: [2024-03-15]
Total Layers: 8  |  Total Thickness: 1.57mm (+/- 10%)
Material: Isola 370HR  |  Dk: 4.04 @ 1GHz  |  Df: 0.012

Layer | Type      | Function    | Cu (oz) | Thickness | Material
------+-----------+-------------+---------+-----------+---------
L1    | Signal    | High-Speed  | 0.5     | 17.5um    | Copper
      | Prepreg   |             |         | 99um      | 2x1080(62%RC)
L2    | Plane     | GND         | 1.0     | 35um      | Copper
      | Core      |             |         | 127um     | 370HR core
L3    | Signal    | General     | 0.5     | 17.5um    | Copper
      | Prepreg   |             |         | 508um     | 2x7628(48%RC)
L4    | Plane     | VCC (split) | 1.0     | 35um      | Copper
      | Core      |             |         | 127um     | 370HR core
L5    | Plane     | GND         | 1.0     | 35um      | Copper
      | Prepreg   |             |         | 508um     | 2x7628(48%RC)
L6    | Signal    | General     | 0.5     | 17.5um    | Copper
      | Core      |             |         | 127um     | 370HR core
L7    | Plane     | VCC2(split) | 1.0     | 35um      | Copper
      | Prepreg   |             |         | 99um      | 2x1080(62%RC)
L8    | Signal    | High-Speed  | 0.5     | 17.5um    | Copper

IMPEDANCE TARGETS:
  Layer 1 (Microstrip): 50 ohm SE @ 5.5mil width, ref L2 GND
  Layer 1 (Diff pair):  100 ohm @ 4.0mil/5.0mil W/S, ref L2 GND
  Layer 3 (Stripline):  50 ohm SE @ 4.5mil width, ref L2+L4
  Layer 3 (Diff pair):  100 ohm @ 3.5mil/5.0mil W/S, ref L2+L4
            

Checkpoint: Assembly Drawings (Top/Bottom)

Assembly Drawing Requirements

• Component outlines: All components shown in their correct position with body outline
• Reference designators: All ref-des readable and adjacent to their component
• Polarity indicators: Pin 1 dots, cathode bands, and positive marks clearly shown
• Board outline: Exact board shape with dimensions
• Fiducial marks: Global and local fiducials identified
• Special instructions: Glue dots, selective soldering areas, conformal coating boundaries
• Scale: 1:1 preferred; if board is too large, show overall at reduced scale + detail views at 1:1
• Revision block: Drawing title, revision, date, approval signatures

Output Verification Workflow

1. Generate all outputs from EDA tool to a dedicated release folder
2. Open ALL Gerbers in a standalone viewer (GerbView, ViewMate, or online viewer):
   • Align all layers using common reference point
   • Verify layer count matches design
   • Check that no layers are accidentally mirrored
   • Verify copper layers show expected patterns
   • Check plane layers (should show anti-pads and clearances correctly)
3. Verify drill alignment: Overlay drill file on copper - hits must center on pads
4. Check mask alignment: Overlay mask on copper - openings must expose all pads
5. Verify board outline: Must be a closed shape on the outline layer
6. Cross-check BOM vs Pick-and-Place: Same component count, same ref-des list
7. Run online DFM check: Upload to fabricator's online checker (JLCPCB, PCBWay offer free DFM analysis)

Complete Output Generation Workflow

Pre-Output Checklist

1. Run final DRC - confirm ZERO violations
2. Regenerate all copper pours / zone fills
3. Re-run DRC after pour regeneration
4. Verify design matches latest schematic (run netlist comparison / ECO check)
5. Lock all component positions (prevent accidental movement)
6. Save design file with version tag

Output Generation Sequence

1. Generate Gerber files (all copper + mask + silk + paste + outline)
2. Generate NC Drill files (PTH, NPTH, blind/buried separately)
3. Generate Pick-and-Place centroid file
4. Generate IPC-D-356 netlist
5. Generate BOM (from schematic, cross-reference with layout)
6. Create/update fabrication drawing
7. Create/update assembly drawings (top + bottom)
8. Create/update stackup specification

Post-Output Verification

1. Open all Gerbers in standalone viewer - visual inspection
2. Verify layer alignment (copper + mask + paste + silk + drill)
3. Check board outline is closed and correct size
4. Verify drill hits align with pads on all layers
5. Spot-check pick-and-place coordinates (minimum 5 per side)
6. Upload to fabricator's online DFM tool for automated checking
7. Package all files into ZIP with readme file listing contents

Common Output Errors