Module 6: Thermal Management

Tj_calculated = Ta_max + (P_dissipated x theta_JA) < Tj_max - 15C for every IC; calculation documented with datasheet references

Power dissipation calculated for all modes (sleep, idle, typical, maximum, burst); worst-case mode identified and used for thermal sizing

Ta_max specified from product requirements (e.g., 55C industrial, 70C automotive); all thermal calculations use this value, not 25C

LDO: P_loss = (Vin - Vout) x Iload_max; Buck: P_loss = Pout x (1/efficiency - 1); calculated at max load and max Vin

P_actual = I^2 x R < P_rated x 0.5 at max ambient; resistors exceeding 100mW individually flagged and package size verified

Power estimated using vendor tool (Xilinx XPE, Intel PowerPlay, or ARM DS) at worst-case toggle rate and clock frequency; not datasheet typical value

Sum of all component dissipation documented; total board dissipation < enclosure thermal capacity with margin; power budget spreadsheet maintained

Board heat map shows W/cm2 density per region; no region exceeds 0.5 W/cm2 without dedicated cooling; hot spots identified and mitigated

Effective theta_JA calculated using board-level conditions (not free-air datasheet value); accounts for PCB copper area, airflow, and adjacent heat sources

Theta_JC (top and bottom) extracted from IC datasheet; correct value used based on primary heat flow path (top-cooled vs. bottom-cooled package)

TIM thermal conductivity >= 3 W/mK; bondline thickness controlled (< 0.1mm for paste, specified for pads); thermal resistance contribution < 20% of total path

IC exposed/thermal pad has solder paste coverage of 50-80% (avoiding voids > 25%); pad connected to ground plane via thermal vias

No unintended air gaps in thermal stack; component coplanarity < 0.05mm; TIM fills all surface roughness and gaps; assembly tolerance analyzed

Complete R_th chain calculated: R_JC + R_TIM + R_heatsink + R_SA; total yields Tj = Ta + (P x R_th_total) < Tj_max with >= 15C margin

Heatsink mounting force 20-80 PSI on TIM interface (per TIM datasheet); spring clip or screw torque spec documented; maintains contact over thermal cycling

R_SA_required = (Tj_max - Ta_max - margin) / P_diss - R_JC - R_TIM; selected heatsink R_SA < R_SA_required at actual airflow conditions

Mounting method (push-pin, screw, clip, adhesive) withstands 30G shock and 10G vibration per product spec; no loosening over thermal cycles

Heatsink fin orientation aligned with airflow direction; no upstream obstructions within 2x fin height; inlet/outlet clearance >= fin spacing

Fan airflow at operating point > system impedance intersection point with >= 20% margin; verified on PQ curve at worst-case system impedance

Fan MTBF > 50,000 hours at max operating temp; tachometer output monitored; thermal throttle or shutdown triggers within 5s of fan failure detection

Heatsink envelope (including fins) clears adjacent components by >= 1mm; clears enclosure walls by >= 2mm; no interference with cables or connectors

Thermal pad rated for continuous operation at Tj_max of component; compressive stress within pad rated range; no pump-out degradation over thermal cycling

PWM fan control with >= 3 thermal zones; speed ramps linearly between T_min (fan start) and T_max (full speed); hysteresis >= 3C to prevent oscillation

N+1 fan redundancy or thermal shutdown within safe Tj limit if single fan fails; system operates within spec with one fan failed in redundant configuration

Thermal via array under QFN/BGA pad has >= 9 vias on 1mm grid; vias filled or capped to prevent solder wicking; via diameter 0.3mm minimum

Vias under solder pads are filled (copper filled, conductive epoxy, or solder plugged) and planarized; open vias in pad cause solder voids > 25%

Copper pour area on outer layers around hot components >= 4x component footprint area; 2oz copper used for power components dissipating > 1W

Internal copper planes (ground/power) continuous under hot components with no splits or voids; plane area provides lateral heat spreading to reduce local hot spots

Tall components (connectors, capacitors > 10mm) placed downstream of hot ICs or offset laterally; no thermal shadowing of critical components

High-power components (regulators, FETs) placed >= 10mm from temperature-sensitive parts (crystals, voltage references, sensors); thermal barrier slots considered

Thermal relief spokes on pads connected to planes: 4 spokes x 0.3mm width minimum for power pads; direct connection (no relief) used for thermal pads requiring maximum heat transfer

Laminate Tg >= max operating temperature + 25C (e.g., Tg170 for 125C operation); Td >= 325C for lead-free reflow; material specified on fab drawing

Tj_calculated at worst case (Ta_max + P_max x theta_JA) is < Tj_max - 15C for all ICs; no component operates above 80% of absolute maximum junction rating

Electrolytic capacitors derated: voltage rating >= 1.5x at max temp; ripple current derated per manufacturer curve at actual temperature; lifetime recalculated using Arrhenius equation

LED Tj < rated Tj_max - 20C at max drive current and Ta_max; lumen maintenance L70 lifetime meets product requirement at operating Tj

Charging disabled below 0C and above 45C; discharging limited above 60C; temperature sensor within 5mm of cell; firmware enforces limits with < 1C hysteresis

Connector housing material rated >= product Ta_max + 20C; contact temperature rise at rated current < 30C; total temperature < material deflection temperature

CTE mismatch stress analyzed for BGA/QFN joints; Coffin-Manson fatigue life > product lifetime x 2 for expected temperature cycling range (delta_T and cycle rate)

Crystal frequency deviation over operating temperature range < interface requirement (e.g., +/-50ppm for USB); parabolic curve checked at temperature extremes, not just 25C

IC thermal shutdown threshold set >= 15C below Tj_abs_max; hysteresis >= 10C to prevent oscillation; shutdown behavior (latch vs auto-recovery) matches system safety requirements

NTC/digital sensors placed within 5mm of each hot spot (processor, regulator, MOSFET); sensor accuracy +/-1C at measurement range; sampling rate >= 1 Hz for thermal control loop

CFD model includes enclosure geometry, fan curves, PCB as anisotropic block, and component power sources; mesh convergence verified (< 2% change with refinement)

FEA conduction model of PCB stack-up uses correct Cu distribution per layer; boundary conditions match actual mounting and airflow; results within 5C of measurement

IR camera measurement of prototype at max load/max ambient confirms all hot spots within 5C of simulation prediction; emissivity calibrated or thermocouple cross-referenced

Prototype tested at: max ambient (thermal chamber) + max load + min airflow (blocked vents or fan at min RPM); all Tj measurements < Tj_max - 10C under these conditions

Margin = Tj_max - Tj_measured at worst case >= 15C for all critical components; margin table maintained in design documentation with pass/fail status per component

Convection cooling derated by air density ratio at max operating altitude (e.g., 80% at 2000m, 65% at 4000m); heatsink R_SA increased proportionally; fan derated per altitude curve

Sealed enclosure: internal air temperature rise calculated (P_total / (h x A_surface)); vented enclosure: vent area provides >= required airflow per chimney effect or fan; solar loading included for outdoor products