Checkpoint 1: All Components Operate at <80% Rated Temperature Critical
Every component must operate with sufficient temperature margin. The 80% rule means no component should exceed 80% of its absolute maximum temperature rating under worst-case conditions. This provides headroom for manufacturing variation, aging, and transient events.
Temperature Derating Guidelines
| Component Type | Max Rated (typical) | 80% Derated Limit | Recommended Margin |
|---|
| Silicon ICs (commercial) | 125°C Tj | 100°C | ≥25°C below max |
| Silicon ICs (industrial) | 150°C Tj | 120°C | ≥30°C below max |
| Power MOSFETs | 150-175°C Tj | 120-140°C | ≥30°C below max |
| Electrolytic capacitors | 85-105°C body | 68-84°C | Every 10°C less = 2× life |
| Ceramic capacitors | 85-125°C | 68-100°C | ≥20°C margin |
| Resistors (thick film) | 155°C body | 124°C | ≥30°C margin |
| Inductors (ferrite) | 125-150°C | 100-120°C | ≥20°C margin |
| Connectors | 105-125°C | 84-100°C | ≥20°C margin |
| PCB substrate (FR4) | Tg=130-180°C | 104-144°C | ≥30°C below Tg |
Step-by-Step Derating Verification
- For each component, determine its absolute maximum temperature rating from the datasheet.
- Calculate the component's operating temperature: T_operating = T_ambient_max + ΔT_self_heating + ΔT_nearby_components.
- Verify: T_operating ≤ 0.8 × T_rated (or T_rated - specified margin, whichever is more conservative).
- For temperature-sensitive components (capacitors, crystals, references), apply stricter derating (60-70%).
- Document derating compliance in a component-by-component thermal analysis spreadsheet.
- Flag any components that fail derating -- either redesign the thermal path or select a higher-rated component.
Example: MCU Temperature Derating Check
Component: STM32F407 (Industrial grade, Tj_max = 105°C)
T_ambient_max = 70°C (product specification)
P_dissipation = 0.4W
Rth_ja = 35°C/W (LQFP-100 on 4-layer board)
T_junction = 70 + 0.4 × 35 = 84°C
Derated limit (80%): 0.8 × 105 = 84°C
EXACTLY at the limit -- no margin!
Solutions:
1. Reduce power (disable unused peripherals): P=0.3W → Tj=80.5°C ✓
2. Improve thermal path (add vias, copper): Rth=28°C/W → Tj=81.2°C ✓
3. Use higher temp grade part (150°C rated): derated to 120°C, plenty of margin ✓
All ICs verified with >20°C margin below rated temperature. Spreadsheet shows worst-case junction temperatures for each IC at 85°C ambient, with thermal resistance based on actual PCB layout (not JEDEC test board values). Temperature-critical components (voltage reference, ADC) placed in cool zones with additional margin.
Engineer assumes "room temperature" (25°C) operation. At 25°C, all components have margin. But the product goes into a 70°C industrial environment. Several components now exceed their rated temperatures. No thermal analysis was done for worst-case ambient.
Checkpoint 2: Electrolytic Capacitor Lifetime vs. Temperature Critical
Electrolytic capacitor lifetime is dominated by temperature. The Arrhenius relationship means lifetime approximately doubles for every 10°C reduction in operating temperature. This makes electrolytics the most temperature-sensitive component in most designs.
Arrhenius Lifetime Model
Electrolytic Capacitor Lifetime Formula:
L_actual = L_rated × 2^((T_rated - T_actual) / 10)
Where:
L_rated = Manufacturer's rated lifetime at T_rated (hours)
T_rated = Rated temperature (°C), typically 85°C or 105°C
T_actual = Actual operating temperature of capacitor body (°C)
Example 1: 105°C, 2000-hour rated capacitor
At 105°C: L = 2000 hours = 83 days (rated)
At 95°C: L = 2000 × 2^1 = 4,000 hours = 167 days
At 85°C: L = 2000 × 2^2 = 8,000 hours = 333 days (~1 year)
At 75°C: L = 2000 × 2^3 = 16,000 hours = 1.8 years
At 65°C: L = 2000 × 2^4 = 32,000 hours = 3.7 years
At 55°C: L = 2000 × 2^5 = 64,000 hours = 7.3 years
At 45°C: L = 2000 × 2^6 = 128,000 hours = 14.6 years
Example 2: Achieving 10-year life requirement
Need: L > 87,600 hours (10 years continuous)
With 105°C/2000hr cap: T_actual ≤ 105 - 10×log₂(87600/2000)
T_actual ≤ 105 - 10×5.45 = 50.5°C
Capacitor body must stay below 50°C for 10-year life!
Capacitor Self-Heating
ESR-based self-heating:
P_cap = I_ripple_RMS² × ESR
ΔT_self = P_cap × Rth_cap (typically 10-30°C/W for small caps)
Example: Input filter capacitor in a buck converter
C = 100µF/50V electrolytic (Nichicon UHE1H101MHD)
ESR = 0.08Ω at 100kHz, 105°C rated, 5000 hours
I_ripple = 1.5A RMS (from converter input current waveform)
P_cap = 1.5² × 0.08 = 0.18W
ΔT_self ≈ 0.18 × 20 = 3.6°C
At Ta=65°C: T_cap = 65 + 3.6 = 68.6°C
L = 5000 × 2^((105-68.6)/10) = 5000 × 2^3.64 = 62,450 hours = 7.1 years
Acceptable for 5-year product, marginal for 10-year.
Selecting Capacitors for Lifetime
- Determine required product lifetime (e.g., 10 years = 87,600 hours at full duty).
- Determine worst-case ambient temperature at the capacitor location.
- Calculate ripple current and self-heating (especially for switching converter caps).
- Calculate actual cap temperature: T_actual = T_ambient + ΔT_self_heating + ΔT_nearby.
- Select cap rated temperature and lifetime to meet: L_rated × 2^((T_rated-T_actual)/10) > Required_life.
- Consider using polymer or ceramic caps where feasible (they don't have electrolyte dry-out failure mode).
Output filter capacitor for LED driver (10-year outdoor life, 65°C ambient): Selected Nichicon UBY series, 105°C/10000hr. At 65°C: L = 10000 × 2^4 = 160,000 hours = 18.3 years. Even with 5°C self-heating (T=70°C): L = 10000 × 2^3.5 = 113,000 hours = 12.9 years. Meets 10-year requirement with margin.
Using cheap 85°C/1000hr electrolytics in a power supply operating at 60°C ambient: L = 1000 × 2^2.5 = 5656 hours = 0.65 years. Capacitors fail (dry out) within 8 months of deployment, causing voltage ripple, regulator instability, and product returns.
- Ignoring ripple current heating: Capacitors near switching converters see significant ripple current. The I²×ESR self-heating can add 5-20°C to the body temperature.
- Measuring ambient, not cap body temperature: The cap body temperature is what matters for lifetime. If it's near hot components, body temp can be 10-20°C above board ambient.
- Using rated life at face value: A "10,000 hour" cap at 105°C gives only 1.14 years at rated temperature! You need to derate to achieve useful field lifetime.
- Polymer caps are not immune: Polymer capacitors don't dry out but do have different aging mechanisms. Their ESR increases over time. Still better than wet electrolytic for lifetime.
Checkpoint 3: MOSFET Safe Operating Area (SOA) at Max Temperature Critical
The MOSFET Safe Operating Area defines the simultaneous voltage and current limits. At elevated temperatures, the SOA boundary shrinks significantly due to increased RDS(on) and reduced thermal margin for secondary breakdown.
SOA Interpretation
SOA Boundaries (from left to right on log-log plot):
1. RDS(on) limit (left boundary):
VDS_max at given ID = ID × RDS(on)
This line slopes upward on log-log plot
2. Maximum current limit (top boundary):
ID_max (package/bond wire limit)
3. Power limit (diagonal boundary):
P_max = VDS × ID = constant for DC
For pulsed: P_max_pulse = P_max_DC × √(t_pulse / t_ref)
4. Thermal instability (secondary breakdown) limit:
Right boundary, more restrictive at high temp
At Tc=25°C: Higher VDS allowed
At Tc=100°C: Boundary moves left (reduced capability)
5. Maximum VDS limit (right boundary):
BVDSS rating
Temperature Derating of SOA
Power Derating:
P_derated = P_max_25°C × (Tj_max - Tj_operating) / (Tj_max - 25°C)
Example: IRFP460 (500V, 20A, Tj_max=150°C)
P_max at 25°C case = 280W
P_max at 100°C case = 280 × (150-100)/(150-25) = 280 × 0.4 = 112W
P_max at 125°C case = 280 × (150-125)/(150-25) = 280 × 0.2 = 56W
SOA Implication:
At VDS=400V (hard switching event), max safe ID:
At 25°C: ID = 280W/400V = 0.7A (DC), or 7A for 100µs pulse
At 100°C: ID = 112W/400V = 0.28A (DC), or 2.8A for 100µs pulse
The 100°C SOA is only 40% of the 25°C value!
Critical SOA Applications
| Application | SOA Concern | Mitigation |
|---|
| Hot-swap controller | Long duration high V×I during inrush | Limit inrush rate, use SOA-rated FETs |
| Motor driver (H-bridge) | Inductive load turn-off spike | Freewheeling diodes, snubbers |
| Linear regulator pass FET | Continuous V×I dissipation | Proper heatsinking, current limiting |
| Load switch | Capacitor inrush at turn-on | Slew rate control, soft-start |
| Switching converter (hard) | Crossover during switching transition | Fast gate drive, soft switching |
- Plot the operating point (VDS, ID) on the SOA curve for your specific MOSFET.
- Use the SOA curve at the expected case/junction temperature, not 25°C.
- For pulsed operation, use the appropriate pulse duration curve (10µs, 100µs, 1ms, 10ms, DC).
- Include a 20% margin from the SOA boundary for manufacturing variation.
- For hot-swap and inrush scenarios, calculate the exact V×I trajectory over time and verify it stays inside SOA at each point.
- Consider using a MOSFET specifically rated for linear-mode operation (SOA-guaranteed) for applications with sustained V×I exposure.
Hot-swap controller design: Input = 48V, load capacitance = 1000µF, MOSFET = IXFN73N30 (SOA guaranteed for linear mode). Inrush limited by gate drive to 5A. VDS during inrush = 48V × (1 - t/RC) with R_sense feedback. Maximum V×I point: 48V × 5A = 240W for 20ms. Verified: SOA at 125°C allows 48V × 8A for 20ms. 60% margin.
Load switch using IRFZ44N: Turning on into 470µF capacitor at 12V. Peak inrush current = 12V/RDS(on) theoretically unlimited. No gate slew control. VDS=12V × ID=50A for 2ms during capacitor charging. SOA at 100°C allows only 12V × 15A for 1ms. MOSFET fails from secondary breakdown during turn-on.
Checkpoint 4: Semiconductor Junction Temperature Margin >15°C Major
All semiconductor junctions must maintain at least 15°C margin below their absolute maximum rated junction temperature. This margin accounts for manufacturing variation, measurement uncertainty, and provides long-term reliability headroom.
Junction Temperature Margin Calculation:
Margin = Tj_max_rated - Tj_operating_worst_case
Required: Margin ≥ 15°C (minimum)
Recommended: Margin ≥ 25°C (for high-reliability applications)
Example: LM317 Voltage Regulator
Tj_max = 125°C (datasheet absolute max)
VIN = 12V, VOUT = 5V, IOUT = 1A
P = (12-5) × 1 = 7W
Package: TO-220 with heatsink, Rth_ja = 12°C/W
Ta = 55°C
Tj = 55 + 7 × 12 = 139°C -- EXCEEDS MAXIMUM!
With better heatsink (Rth_ja = 8°C/W):
Tj = 55 + 7 × 8 = 111°C
Margin = 125 - 111 = 14°C -- STILL BELOW 15°C REQUIREMENT
Need: Rth_ja ≤ (125-15-55)/7 = 7.86°C/W or reduce power
Temperature Margin by Application Class
| Application Class | Min Margin | Rationale |
|---|
| Consumer (1-3 year life) | 15°C | Standard reliability, benign environment |
| Industrial (5-10 year life) | 20°C | Extended life, moderate environment |
| Automotive (15+ year life) | 25°C | Harsh environment, high reliability |
| Military/Aerospace | 30°C | Mission-critical, extreme conditions |
| Medical (life-critical) | 25°C | Safety margin for patient protection |
Power MOSFET thermal budget: Tj_max = 150°C. Target Tj at worst case = 120°C (30°C margin). Ta_max = 85°C. Allowable ΔT = 35°C. P_total = 3W. Required Rth_ja = 35/3 = 11.7°C/W. Actual Rth_ja = 9.5°C/W (with thermal vias and copper pour). Tj_actual = 85 + 3×9.5 = 113.5°C. Margin = 36.5°C. Excellent.
"Typical" analysis: Using typical power (not max), typical ambient (25°C, not 85°C), and JEDEC Rth_ja (not actual board). Shows 50°C margin. But worst-case: max power × actual Rth × max ambient = 148°C. Only 2°C below absolute maximum. One hot day causes field failures.
Checkpoint 5: Connector Current Derated for Temperature Major
Connector current ratings are typically specified at 25°C or 30°C ambient. At elevated temperatures, the current must be derated because the temperature rise (I²R heating) plus ambient must not exceed the connector's maximum operating temperature.
Connector Current Derating Formula:
I_derated = I_rated × √((T_max - T_ambient) / (T_max - T_ref))
Where:
I_rated = Current rating at reference temperature T_ref
T_max = Maximum connector temperature (typically 105-125°C)
T_ambient = Actual operating ambient temperature
T_ref = Reference temperature for the rating (typically 25°C)
Example: Molex Micro-Fit 3.0 (rated 5A at 25°C, max 105°C)
At 25°C: I = 5A (full rating)
At 50°C: I = 5 × √((105-50)/(105-25)) = 5 × √(55/80) = 5 × 0.829 = 4.15A
At 70°C: I = 5 × √((105-70)/(105-25)) = 5 × √(35/80) = 5 × 0.661 = 3.3A
At 85°C: I = 5 × √((105-85)/(105-25)) = 5 × √(20/80) = 5 × 0.5 = 2.5A
At 85°C ambient, the 5A connector can only carry 2.5A!
Additional Derating Factors
| Factor | Derating | Notes |
|---|
| Adjacent pins loaded | ×0.7-0.8 | When all pins carry max current simultaneously |
| High altitude (>2000m) | ×0.85-0.95 | Reduced convection cooling |
| Mating cycles (worn) | ×0.9-0.95 | Increased contact resistance after 100+ cycles |
| PCB-mount (vs. cable) | ×0.8-0.9 | PCB thermal impedance limits heat removal |
| Enclosed (no airflow) | ×0.7-0.8 | Air pocket traps heat around connector |
12V power input connector (Molex Mini-Fit Jr, rated 9A/pin at 25°C): Application draws 6A continuous at 55°C ambient. Derating: I_max = 9 × √((105-55)/80) = 9 × 0.79 = 7.1A. Using 2 pins paralleled: capacity = 14.2A. Load/capacity = 6/14.2 = 42%. Well within limits. Also verified: mating force and retention adequate for vibration.
Single-pin connector rated 3A (at 25°C) used to supply 2.8A in an 80°C enclosure. Derated capacity: 3 × √((105-80)/80) = 3 × 0.559 = 1.68A. Actual load exceeds derated capacity by 67%! Connector overheats, plastic melts, potential fire hazard.
Checkpoint 6: Resistor Power Derated per Curve Minor
Resistors must be derated at elevated temperatures per the manufacturer's derating curve. Standard thick-film resistors typically derate linearly from 70°C to zero power at 155°C (maximum element temperature).
Standard Resistor Derating Curve (thick-film chip):
For T ≤ 70°C: P_allowed = P_rated (full power)
For 70°C < T < 155°C: P_allowed = P_rated × (155 - T) / (155 - 70)
For T ≥ 155°C: P_allowed = 0
Example: 0805, 0.125W rated
At 25°C: P_allowed = 125mW
At 70°C: P_allowed = 125mW (derating starts here)
At 85°C: P_allowed = 125 × (155-85)/85 = 125 × 0.824 = 103mW
At 100°C: P_allowed = 125 × (155-100)/85 = 125 × 0.647 = 81mW
At 125°C: P_allowed = 125 × (155-125)/85 = 125 × 0.353 = 44mW
Design check: A 100mW load in a 0805 at 90°C ambient:
P_allowed at 90°C = 125 × (155-90)/85 = 95.6mW
100mW > 95.6mW -- EXCEEDS DERATED RATING!
Need 1206 (250mW): at 90°C = 250×0.765 = 191mW > 100mW ✓
Derating by Resistor Type
| Resistor Type | Full Power Limit | Zero Power | Notes |
|---|
| Thick-film chip (standard) | 70°C | 155°C | Most common, lowest cost |
| Thin-film chip (precision) | 70°C | 155°C | Same derating as thick-film |
| Wirewound (power) | 25°C or 70°C | 275-350°C | Higher temperature capability |
| Metal foil (precision) | 70°C | 175°C | Slightly better than thick-film |
| Current sense (metal strip) | 70°C | 170°C | Low TCR, high pulse power |
Combined Voltage + Power Derating:
Both power AND voltage limits must be respected:
0402: 50V max, 63mW
0603: 75V max, 100mW
0805: 150V max, 125mW
1206: 200V max, 250mW
2512: 200V max, 1W
Example: 10kΩ 0603 on a 48V rail
P = V²/R = 48²/10000 = 0.23W -- EXCEEDS 100mW RATING!
Also: V = 48V < 75V voltage limit ✓
Power is the limiting factor. Need 1206 or larger.
Design rule: All resistors used at ≤50% of their derated power at maximum ambient temperature. For 85°C ambient, 0805: P_allowed = 125 × (155-85)/85 × 0.5 = 51.5mW maximum design load. Any resistor exceeding this threshold is upsized to the next package.
Current-sense resistor (10mΩ, 2512, 1W rated) carrying 8A: P = 8² × 0.01 = 0.64W. At 25°C: 0.64W < 1W, seems fine. But at 100°C ambient: P_allowed = 1W × (155-100)/85 = 0.647W. The 0.64W is at 99% of derated capacity -- essentially no margin. Self-heating raises element temp further, creating a borderline condition.
- Self-heating creates a feedback loop: Power dissipation heats the resistor, which reduces the allowed power. For borderline cases, iterate: P→T_rise→T_actual→P_allowed until convergence.
- Surge/pulse derating is separate: Thick-film resistors have peak voltage limits for pulse events (ESD, transients) that are often lower than the steady-state voltage rating.
- Substrate temperature vs. ambient: The derating temperature is the resistor body/substrate temperature, not the room ambient. If the resistor is near a hot IC, its base temperature may be 30°C above room ambient.
- Resistor arrays share substrate heat: A 4-resistor array with all elements loaded at rated power will overheat because the total power exceeds the package rating.
