Checkpoint 1: Junction-to-Ambient Thermal Path Defined (Rth_ja) Critical
Every heat-generating component must have a clearly defined thermal path from its semiconductor junction (or hottest internal point) to the ambient air. This path is characterized by a chain of thermal resistances that determines the final junction temperature.
The Thermal Resistance Network
Fundamental Equation:
Tj = Ta + P × Rth_ja
Where:
Tj = Junction temperature (°C)
Ta = Ambient temperature (°C)
P = Power dissipated (W)
Rth_ja = Total thermal resistance, junction to ambient (°C/W)
Expanded thermal resistance chain:
Rth_ja = Rth_jc + Rth_cs + Rth_sa
Rth_jc = Junction to case (package property, from datasheet)
Rth_cs = Case to sink/board (interface material)
Rth_sa = Sink/board to ambient (convection + radiation)
Step-by-Step Tutorial
- Identify the primary thermal path: Is heat removed from the top (heatsink), bottom (PCB), or both? Check the package datasheet for Rth_jc_top vs. Rth_jc_bottom.
- Determine the thermal resistance of each element in the chain from the datasheet and material properties.
- Calculate the total Rth_ja for your specific board design. The datasheet Rth_ja is measured on a specific JEDEC test board and may not match your actual PCB.
- Verify: Tj = Ta_max + P_max × Rth_ja_actual < Tj_rated (with margin).
- If Tj exceeds limits, identify which resistance in the chain is dominant and optimize that element.
- Document the thermal path design with a thermal resistance network diagram.
Typical Package Thermal Resistances
| Package | Rth_jc (°C/W) | Rth_ja JEDEC (°C/W) | Rth_ja with pours (°C/W) | Notes |
|---|
| SOT-23 | 80-120 | 200-300 | 150-200 | Limited by small pad area |
| SOT-223 | 15-25 | 50-80 | 40-60 | Tab connects to inner plane |
| SOIC-8 | 30-50 | 100-150 | 70-100 | Exposed pad version much better |
| QFN-24 (4×4mm) | 3-8 | 35-50 | 20-30 | Requires thermal pad connection |
| QFN-48 (7×7mm) | 1-3 | 20-30 | 12-18 | Large thermal pad, via array needed |
| BGA-256 (17×17mm) | 0.5-2 | 15-25 | 8-15 | Multiple thermal paths through balls |
| TO-220 | 1-3 | 50-65 | 30-40 | Best with heatsink (Rth_ja=5-15) |
| D²PAK (TO-263) | 1-3 | 40-60 | 15-25 | Large tab to PCB copper |
Example: LM3940 LDO in SOT-223
P_dissipated = (5.0V - 3.3V) × 1.0A = 1.7W
Rth_ja (datasheet, JEDEC board) = 53°C/W
Rth_ja (actual board, 1oz Cu, 2 layer) = 65°C/W
Rth_ja (actual board, 2oz Cu, 4 layer, pours) = 42°C/W
At Ta = 70°C:
Tj = 70 + 1.7 × 42 = 141.4°C (4-layer) -- Marginal for 150°C rating
Tj = 70 + 1.7 × 65 = 180.5°C (2-layer) -- EXCEEDS MAXIMUM!
Thermal path for a QFN-48 motor driver (3W dissipation): Rth_jc = 2°C/W via exposed pad. Thermal pad connected through 25 vias (0.3mm drill) to a 40×40mm ground plane on layer 2. Ground plane also connected to layers 3 and 4. Calculated Rth_ja = 15°C/W. Tj = 85 + 3×15 = 130°C, within 150°C limit with 20°C margin.
QFN package with exposed thermal pad but no vias underneath -- the thermal pad is only connected to the top layer copper. Rth_ja increases from 15°C/W to 45°C/W because heat cannot spread to inner planes. Tj = 85 + 3×45 = 220°C -- catastrophic failure.
- Using datasheet Rth_ja directly: The JEDEC test board (1s0p or 2s2p) rarely matches your actual PCB. Always calculate based on your specific stack-up and copper area.
- Ignoring the board-level contribution: For packages without heatsinks, 70-90% of heat is removed through the PCB. Board design is the thermal design.
- Parallel paths: In reality, heat flows simultaneously through top (convection), bottom (PCB), and sides. Use parallel resistance: 1/Rth_total = 1/Rth_top + 1/Rth_bottom + 1/Rth_sides.
- Confusing Rth_jc and Rth_ja: Rth_jc is only meaningful if you have a heatsink on the case. Without a heatsink, you need the full Rth_ja.
Checkpoint 2: Thermal Pad Connected to Inner Planes Critical
Exposed thermal pads (also called exposed die pads or EPADs) on QFN, DFN, QFP, and BGA packages must be properly connected to internal copper planes to provide an effective heat conduction path.
Step-by-Step Tutorial
- Identify the thermal pad size from the package drawing (recommended land pattern in the datasheet).
- Create a copper pad on the top layer matching the recommended land pattern size (typically 80-100% of the exposed pad area).
- Connect this pad to an internal ground or power plane using thermal vias (see Checkpoint 3).
- Ensure the internal plane extends at least 3-5mm beyond the component footprint in all directions for heat spreading.
- Verify solder paste coverage: Use a divided pad pattern or windowed stencil to prevent solder voids and component floating.
- Confirm the pad is properly defined in the PCB library with correct paste mask and solder mask layers.
Solder Paste Pattern for Thermal Pads
Paste Coverage Guidelines:
Target: 50-75% paste coverage on thermal pad
Pattern: Divide into grid of smaller rectangles
Example: 5mm × 5mm thermal pad
Divide into 3×3 grid of 1.4mm × 1.4mm paste openings
Gap between openings: 0.25mm
Effective coverage: (1.4×1.4×9) / (5×5) = 70.6%
Stencil thickness for thermal pad: Match component side (typ 0.125mm)
Too much paste → component floats, poor coplanarity
Too little paste → voids, high Rth_cs
QFN-32 (5×5mm) with 3.5×3.5mm exposed pad: Top copper pad = 3.5×3.5mm. Paste mask divided into 4×4 grid of 0.7mm squares with 0.15mm gaps (65% coverage). Pad connected to ground plane on Layer 2 via 16 thermal vias (0.3mm drill, 0.6mm pad). Solder mask opening 0.1mm larger than copper pad on each side.
Thermal pad created as a single large paste opening (100% coverage). During reflow, excessive solder causes the IC to float 0.1mm above the board, creating open connections on corner pads. Additionally, large solder volume creates voids (>50%) that dramatically increase thermal resistance.
- Via-in-pad without fill: Open vias in the thermal pad wick solder away during reflow, creating voids underneath and solder balls on the bottom. Either fill and plate vias, or cap them from the bottom.
- Insufficient solder mask dam: Without solder mask between thermal vias and component pads, solder can bridge causing shorts. Maintain 0.1mm minimum solder mask dam.
- Forgetting paste on thermal pad: Some CAD libraries omit paste on the thermal pad by default. Always verify paste layer coverage.
- Ground plane discontinuity: If the inner ground plane has large splits or cutouts under the thermal pad, heat spreading is compromised.
Checkpoint 3: Thermal Via Array Under Exposed Pads Critical
Thermal vias transfer heat from the exposed pad on the top layer through to internal planes and the bottom of the board. The via array design directly determines the thermal resistance of this path.
Thermal Via Design Rules
Single Via Thermal Resistance:
Rth_via = L / (k × A × n)
Where:
L = Board thickness traversed by via (mm)
k = Thermal conductivity of via material:
- Copper plating: 385 W/(m·K)
- Solder-filled: 50 W/(m·K)
- Air (unfilled): 0.025 W/(m·K) -- negligible
A = Cross-sectional area of copper in via (mm²)
n = Number of vias
For a plated via (not filled):
A_copper = π × (D_outer² - D_inner²) / 4
A_copper = π × ((0.6mm)² - (0.3mm)²) / 4 = 0.212 mm²
(D_outer = pad_dia for land, D_inner = drill_dia)
Actually: A_copper = π × d × t (annular plating)
d = drill diameter = 0.3mm, t = plating thickness = 0.025mm
A_copper = π × 0.3 × 0.025 = 0.0236 mm²
Example: Via Array Thermal Resistance Calculation
Board thickness: 1.6mm
Via drill: 0.3mm, plating: 25µm copper
Number of vias: 16 (4×4 array)
A_single = π × 0.3mm × 0.025mm = 0.02356 mm²
A_total = 16 × 0.02356 = 0.377 mm²
Convert: 0.377 mm² = 0.377 × 10⁻⁶ m²
Rth = L / (k × A)
Rth = 0.0016m / (385 W/m·K × 0.377×10⁻⁶ m²)
Rth = 0.0016 / 0.0001451 = 11.0 °C/W
With solder-filled vias:
A_solder = π × (0.3mm)² / 4 × 16 = 1.131 mm²
Rth_solder = 0.0016 / (50 × 1.131×10⁻⁶) = 28.3 °C/W
Rth_combined (copper + solder fill): ~8.0 °C/W
Optimal Via Array Configuration
| Parameter | Recommended | Minimum | Notes |
|---|
| Via drill diameter | 0.3mm (12mil) | 0.2mm (8mil) | Smaller = more vias possible |
| Via pad diameter | 0.6mm (24mil) | 0.45mm (18mil) | Must meet annular ring rules |
| Via pitch | 1.0mm (40mil) | 0.8mm (32mil) | Tighter = better thermal but harder to fab |
| Via fill | Copper-filled + plated over | Solder-filled or capped | Filled vias essential for via-in-pad |
| Array coverage | 80% of thermal pad area | 50% | Leave edge for solder mask dam |
| Minimum number | 9-25 per pad | 5 | More is better up to practical limit |
- Determine the thermal pad dimensions from the component datasheet.
- Calculate via pitch: Start with 1.0mm, adjust tighter if space allows and fabrication supports it.
- Determine via count: Fill the thermal pad area with vias at the chosen pitch, leaving 0.2mm from pad edges.
- Specify via type: For QFN/BGA, use filled and plated-over vias (IPC Type VII) to prevent solder wicking.
- Connect vias to the nearest ground/power plane (typically Layer 2 in a 4-layer board). Also connect to Layer 3 and 4 for maximum spreading.
- Add bottom-side copper pour under the via array for additional heat spreading and radiation.
QFN-48 (7×7mm) with 5.2×5.2mm thermal pad: 25 vias (5×5 array) at 1.0mm pitch, 0.3mm drill, filled with copper and plated over. Connected to solid ground plane on L2 (0.2mm below surface). Thermal pad divided into 5×5 paste segments. Calculated Rth_via = 4.4°C/W. Total Rth_jc + Rth_via + Rth_board_to_air = 2 + 4.4 + 15 = 21.4°C/W.
Only 4 vias placed at corners of a 5×5mm thermal pad. Via drill = 0.2mm with standard plating (no fill). Open vias allow solder to wick through during reflow, creating solder balls on the bottom layer. Thermal resistance of via array = 85°C/W -- barely better than no vias at all.
Checkpoint 4: Thermal Interface Material (TIM) Specified Major
When a heatsink or heat spreader is used, the thermal interface material between the component and heatsink is critical. Even small air gaps create enormous thermal resistance due to air's very low thermal conductivity (0.025 W/m·K).
TIM Types and Properties
| TIM Type | Thermal Conductivity (W/m·K) | Thickness (mm) | Rth (°C·cm²/W) | Application |
|---|
| Thermal grease (silicone) | 0.7-5 | 0.025-0.05 | 0.05-0.2 | Heatsink-to-IC, best performance |
| Thermal grease (metal oxide) | 3-8 | 0.025-0.05 | 0.02-0.1 | High-performance applications |
| Phase-change material | 0.7-4 | 0.025-0.05 | 0.05-0.15 | Pre-applied, melts at operating temp |
| Thermal pad (soft) | 1-6 | 0.5-5.0 | 0.5-5.0 | Gap filling, tolerance absorption |
| Graphite sheet | 5-10 (through), 400-1500 (in-plane) | 0.025-0.1 | 0.05-0.2 | Heat spreading, EMI shielding |
| Indium foil | 86 | 0.05-0.25 | 0.005-0.03 | Highest performance, expensive |
| Thermal adhesive | 1-3 | 0.05-0.1 | 0.1-0.5 | Permanent attachment |
TIM Thermal Resistance Calculation:
Rth_TIM = BLT / (k × A)
Where:
BLT = Bond Line Thickness (m) -- actual compressed thickness in use
k = Thermal conductivity of TIM (W/m·K)
A = Contact area (m²)
Example: Thermal pad between IC and heatsink
TIM: Bergquist Gap Pad 5000S35 (k = 5.0 W/m·K)
Thickness: 1.0mm (compressed to 0.8mm under mounting pressure)
Contact area: 20mm × 20mm = 400 mm² = 4×10⁻⁴ m²
Rth_TIM = 0.0008 / (5.0 × 4×10⁻⁴) = 0.4 °C/W
Compare to thermal grease on same area:
BLT = 0.05mm, k = 3.5 W/m·K
Rth_grease = 0.00005 / (3.5 × 4×10⁻⁴) = 0.036 °C/W
Grease is 11× better! But pads are easier to apply in production.
- Determine the gap to be filled: Measure or calculate the distance between the component top/bottom and the heatsink surface, including tolerance stack-up.
- Select TIM type based on gap size: Grease/phase-change for <0.1mm, soft pads for 0.5-5mm, putty for irregular shapes.
- Verify mounting pressure: Most TIMs require a specific pressure (typically 10-100 psi) for rated performance. Ensure your mounting method provides this.
- Calculate Rth_TIM and add to the thermal resistance chain.
- Specify the exact TIM part number, dimensions, and application method in the BOM and assembly drawing.
- Consider long-term reliability: Thermal grease can pump-out under thermal cycling. Phase-change and pads are more stable.
FPGA thermal solution: Using Laird Tflex 700 thermal pad (k=6.0 W/m·K, 1.5mm thick) between BGA package top and chassis heatsink. Pad selected to accommodate 1.0-2.0mm tolerance variation. Compressed thickness at mounting force = 1.2mm. Rth_TIM = 0.0012/(6.0×0.0009) = 0.22°C/W. Contact area = 30×30mm. Assembly drawing specifies exact pad dimensions and placement.
Using "generic thermal paste" (no part number specified) between a power MOSFET and heatsink. The paste is not specified in the BOM, so production uses whatever is on hand. Some batches use a k=0.5 W/m·K paste instead of the k=4 W/m·K paste used in prototyping. Thermal performance degrades 8× and MOSFETs fail in the field.
- Assuming zero-thickness interface: Even thermal grease has a bond line thickness of 25-50µm. This adds to Rth.
- Ignoring contact resistance: Surface roughness creates additional resistance beyond bulk material conductivity. Actual TIM performance includes this.
- Thermal pad compression: Under-compressed pads have poor contact. Over-compressed pads squeeze out. Use the manufacturer's recommended pressure range.
- Pump-out effect: Thermal cycling causes grease migration over time. After 1000+ thermal cycles, grease-based solutions can degrade significantly.
Checkpoint 5: Heat Spreading Copper Pour Adequate Major
Copper pours on PCB layers serve as heat spreaders, distributing concentrated heat from components over a larger area for convection and radiation to the ambient. The size and configuration of these pours directly impacts thermal performance.
Copper Spreading Resistance
Spreading Resistance (simplified, circular source on rectangular plate):
Rth_spread ≈ 1 / (π × k × d_eff)
Where:
k = Copper thermal conductivity = 385 W/(m·K)
d_eff = Effective diameter of the heat source (m)
More accurate (Kennedy's formula for constriction):
Rth_spread = (1 - 1.41ε + 0.344ε³ + 0.043ε⁵ + 0.179ε⁷) / (4 × k × a)
where ε = a/b (ratio of source radius a to spread radius b)
Example: 5mm × 5mm QFN on 50mm × 50mm copper pour (1oz)
Copper thickness: 35µm (1oz)
Source area: 5×5mm (equivalent radius a = 2.82mm)
Spread area: 50×50mm (equivalent radius b = 28.2mm)
ε = 2.82/28.2 = 0.1
Thin-plate spreading resistance:
Rth_spread ≈ ln(b/a) / (2π × k × t)
Rth_spread = ln(28.2/2.82) / (2π × 385 × 0.000035)
Rth_spread = 2.303 / 0.0847 = 27.2 °C/W (single layer, 1oz)
Effective Copper Pour Thermal Conductance:
For a 4-layer board with thermal vias:
Layer 1: 1oz copper, 35µm → k×t = 385 × 0.035 = 13.5 W·mm/K
Layer 2: 1oz copper (ground plane) → 13.5 W·mm/K
Layer 3: 0.5oz copper (signal) → 6.75 W·mm/K
Layer 4: 1oz copper → 13.5 W·mm/K
Effective: Σ(k×t) = 47.25 W·mm/K (all layers contributing)
Equivalent single layer: 47.25/385 = 0.123mm = ~3.5oz copper equivalent
This is why multi-layer boards cool much better than 2-layer!
Minimum Copper Pour Sizing
| Power (W) | Min Pour Size (1oz, 2L) | Min Pour Size (1oz, 4L) | Estimated Rth_sa (°C/W) |
|---|
| 0.5 | 15×15mm | 10×10mm | 80-100 |
| 1.0 | 25×25mm | 15×15mm | 50-70 |
| 2.0 | 40×40mm | 25×25mm | 30-45 |
| 5.0 | 70×70mm | 45×45mm | 15-25 |
| 10.0 | Heatsink needed | 65×65mm | 10-15 |
Power MOSFET (2W dissipation) in D²PAK: Drain pad connected to 30×30mm copper pour on top layer, with 20 vias connecting to an unbroken ground plane on Layer 2. Layer 2 plane extends 40×40mm around the MOSFET. Bottom layer has exposed copper (no solder mask) in the same area for enhanced radiation. Measured Rth_ja = 22°C/W.
Same MOSFET but copper pour is only 8×10mm (barely larger than the component). Multiple signal traces cut through the pour creating thermal bottlenecks. Ground plane on L2 has a split directly under the component for signal routing. Actual Rth_ja = 55°C/W -- component overheats.
- Copper pour fragmentation: Signal traces cutting through a thermal pour create high-resistance bottlenecks. Route signals around thermal zones.
- Insufficient inner plane connection: A top pour without via connections to inner planes is only using 35µm of copper. Via stitching throughout the pour is essential.
- Solder mask over thermal areas: Solder mask (thermal conductivity ~0.2 W/m·K) is an insulator. Consider opening solder mask on non-populated thermal areas for better radiation and convection.
- Isolated copper islands: Small copper islands not connected to the thermal pour provide negligible benefit. Ensure continuous copper paths.
Checkpoint 6: Thermal Stack-up (Rth Chain) Calculated Critical
The complete thermal resistance chain from junction to ambient must be calculated by summing all series resistances and combining parallel paths. This final calculation confirms whether the thermal design meets requirements.
Complete Thermal Network Example
Example: QFN-48 Motor Driver, 4W dissipation, 4-layer PCB
Path 1 (through PCB - primary):
Rth_jc_bottom = 2.0 °C/W (junction to exposed pad)
Rth_solder = 0.5 °C/W (solder joint under thermal pad)
Rth_vias = 4.0 °C/W (16 vias, 0.3mm drill, 1.6mm board)
Rth_spreading = 8.0 °C/W (30mm×30mm pour, 4 layers)
Rth_board_to_air = 25 °C/W (natural convection from board)
Total Path 1: 39.5 °C/W
Path 2 (through top - secondary):
Rth_jc_top = 15 °C/W (junction to package top)
Rth_package_to_air = 100 °C/W (natural convection from 7×7mm top)
Total Path 2: 115 °C/W
Combined (parallel paths):
1/Rth_total = 1/39.5 + 1/115 = 0.0253 + 0.0087 = 0.034
Rth_total = 29.4 °C/W
Junction Temperature:
Tj = Ta + P × Rth_total = 85 + 4 × 29.4 = 202.6°C
EXCEEDS 150°C MAXIMUM! Need heatsink or reduced power.
With Heatsink Added (Path 3):
Rth_jc_top = 15 °C/W
Rth_TIM = 1.5 °C/W (thermal pad, k=3 W/m·K, 0.5mm, 15×15mm area)
Rth_heatsink = 8 °C/W (small extruded aluminum, natural convection)
Total Path 3: 24.5 °C/W
Combined with PCB path:
1/Rth_total = 1/39.5 + 1/24.5 = 0.0253 + 0.0408 = 0.0661
Rth_total = 15.1 °C/W
Tj = 85 + 4 × 15.1 = 145.4°C
Marginal. Consider forced airflow or larger heatsink.
- Draw the complete thermal resistance network showing all parallel and series paths from junction to ambient.
- Assign values to each resistance element from datasheets, calculations, or empirical data.
- Solve the network: series resistances add, parallel paths combine as reciprocals.
- Calculate Tj at maximum ambient temperature and maximum power dissipation.
- Verify Tj < Tj_max with at least 15°C margin (for safety and reliability).
- If margin is insufficient, identify the largest resistance in the dominant path and optimize it.
Complete thermal stack-up documented in a spreadsheet: Each component has its own row with all Rth values, calculated Tj at three ambient temperatures (25°C/55°C/85°C), and clear pass/fail status. The stack-up is updated whenever the layout changes and is reviewed at each design gate.
Thermal analysis done only for the "obvious" high-power components (main regulator and processor), ignoring smaller ICs. A 500mW op-amp in SOT-23-5 (Rth_ja=220°C/W) runs at Tj = 85 + 0.5×220 = 195°C -- well above its 150°C limit. This was missed because the component seemed "low power."
