Tutorial 5.5 - Power Distribution Layout

Introduction to Power Distribution Layout

The Power Distribution Network (PDN) must deliver clean, stable power to every IC on the board with minimal voltage drop and noise. A poorly designed PDN is the root cause of many "mysterious" signal integrity and EMC failures. The layout of power planes, traces, vias, and decoupling capacitors directly determines PDN impedance from DC to GHz frequencies.

PDN Design Hierarchy

VRM (Voltage Regulator): Controls DC voltage, handles load transients up to ~100 kHz
Bulk capacitors: Energy storage for medium-frequency transients (100 kHz - 10 MHz)
Local decoupling capacitors: High-frequency current source (10 MHz - 500 MHz)
Plane capacitance: Ultra-high-frequency decoupling (>500 MHz, from tightly-coupled plane pairs)
On-die capacitance: IC's internal decoupling (highest frequency, fixed by IC design)

Checkpoint: Power Plane Shapes Adequate

Review Criteria

Power plane shapes (polygons) cover the entire area needed by their load components. No isolated islands exist. Plane shapes have adequate copper area for current capacity and low impedance. Multiple voltage domains are properly separated with appropriate clearance.

Power Plane Design Rules

Coverage: Power plane should extend beyond the furthest load component by at least 5mm in all directions
Width at narrowest point: Calculate based on maximum current and acceptable voltage drop
Clearance between power domains: Minimum 20 mil (0.5mm) for low-voltage; per IPC-2221 for higher voltages
Thermal relief on connections: Use direct connections (no thermal relief) for power vias to minimize resistance
No isolated islands: Every portion of a power shape must connect to the source

Voltage Drop Calculation for Power Traces

DC Resistance of a trace:
  R = rho * L / (W * T)

Where:
  rho = resistivity of copper = 1.68e-8 ohm*m (at 20C)
  L = trace length (m)
  W = trace width (m)
  T = copper thickness (m)

Voltage drop:
  V_drop = I * R = I * rho * L / (W * T)

Example: 2A through 50mm trace, 10mil wide, 1oz copper (35um):
  R = 1.68e-8 * 0.05 / (0.000254 * 0.000035) = 94.5 milliohm
  V_drop = 2 * 0.0945 = 189 mV (UNACCEPTABLE for 1.0V rail!)

Fix: Use 100mil trace or dedicate a power plane region:
  R = 1.68e-8 * 0.05 / (0.00254 * 0.000035) = 9.45 milliohm
  V_drop = 2 * 0.00945 = 18.9 mV (acceptable)

Current Density Visualization

Modern EDA tools provide current density analysis that shows hotspots in power distribution:

Altium Designer - PDN Analyzer

Use Tools > Power Distribution Network (PDN) Analyzer. Define source (regulator output) and sinks (IC power pins with current draw). The tool calculates DC voltage drop across the entire plane shape and highlights bottlenecks in red. Target: less than 3% voltage drop from source to any sink.

Cadence Allegro - PowerDC/Sigrity

Use Analyze > IR Drop (requires Sigrity integration). Provides detailed current density maps showing A/mm2 across all copper. Identifies pinch points where via anti-pads or plane splits create current bottlenecks. Export results as overlay on PCB view.

KiCad - External Tools

KiCad does not have built-in PDN analysis. Use external tools: (1) Export copper geometry as DXF, import into field solver. (2) Use free tools like Saturn PCB Toolkit for trace calculations. (3) Consider open-source PDN solvers or commercial tools like Ansys SIwave (imports ODB++).

Good: Well-Designed Power Shape

1.8V DDR power plane is a solid polygon on Layer 4 covering the entire DRAM region plus 10mm margin. Width never narrows below 5mm. Direct via connections (no thermal relief) to all VDDQ pins. Bulk capacitors at the plane entry point. DC drop simulation shows less than 10mV from regulator to furthest DRAM.

Bad: Bottlenecked Power

1.8V power is a narrow (1mm) trace that snakes between components instead of a wide plane pour. At one point it necks down to 0.3mm between two via clusters. Simulation shows 85mV drop at the far end (4.7% of 1.8V). DRAM timing margin is compromised by power supply noise.

Checkpoint: No Bottlenecks in Power Paths

Review Criteria

Power planes and traces maintain adequate width throughout their path from source to all loads. No pinch points exist where copper narrows due to via anti-pads, routing channels, or board edge proximity.

Common Bottleneck Locations

Between via arrays: Dense via clusters create anti-pad "Swiss cheese" that fragments the plane
At plane splits: Where one voltage domain borders another, the channel between them narrows
Near board edges: Plane pullback (typically 20mil from edge) reduces effective width
Under BGA components: Dense signal via field fragments the underlying power plane
At connector transitions: Power from connector pin must spread from a single point to a wide plane

How to Identify Bottlenecks

Run DC IR-drop simulation (if available in your EDA tool)
Visually inspect power plane shapes with all other layers visible (to see via clearances)
Trace the power path from regulator output to each major load - note any narrowing
Check that via anti-pads do not create less than 50% copper remaining at any cross-section
Verify power plane under BGA has adequate copper for the IC's total current draw

Common Pitfall: Signal Via Field Fragmenting Power Plane

A large BGA has 200 signal vias passing through the power plane layer. Each via's anti-pad removes 0.6mm diameter of copper. In dense areas, the plane is reduced to thin copper bridges between anti-pads (sometimes less than 0.1mm). This creates a high-impedance power distribution at the IC that needs the most current. Solution: Route critical power shapes around the via field, use wider plane sections, or add power vias that feed directly to the IC power pins through the via field.

Checkpoint: Decoupling Cap Via Placement Optimal

Review Criteria

Decoupling capacitor vias are placed to minimize the current loop area between the capacitor and the IC power/ground pins. The via is positioned on the IC side of the capacitor pad (not the far side). Via connections to planes are direct (no thermal relief).

Optimal Via Placement Patterns

Pattern 1: Via on IC side (BEST for loop area)

  [IC Pin] ---short--- [Via] ---plane--- [Cap Pad 1]
                                          [   Cap   ]
  [IC Pin] ---short--- [Via] ---plane--- [Cap Pad 2]

  Loop area: Minimal (via-to-IC distance dominates)

Pattern 2: Shared via between IC and Cap (GOOD)

  [IC Pin] ---[Via]--- Cap Pad 1]
                       [   Cap   ]
  [IC Pin] ---[Via]--- [Cap Pad 2]

  Via serves both the IC power pin escape AND cap connection.
  Best possible loop area - essentially zero trace between cap and IC.

Pattern 3: Via on far side of cap (COMMON BUT WORSE)

  [IC Pin] ---trace--- [Cap Pad 1]
                        [   Cap   ]
                        [Cap Pad 2] ---[Via]---plane

  Loop includes the full cap body length + trace to IC.
  Adds 1-3mm to the loop. Still functional but suboptimal.

Critical Rules for Decoupling Via Connections

No thermal relief: Power/ground vias for decoupling must use direct/solid connections to plane, not thermal spokes (thermal relief adds 0.3-0.5 nH inductance)
Minimum via count: Each cap needs minimum 2 vias (one power, one ground). Two vias per pad is ideal for high-frequency performance
Via placement order: GND via closer to IC than power via (ground loop is more critical)
Via size: 0.3mm drill minimum for adequate current; larger is not better (increases anti-pad, reduces plane copper)

Good: Optimized Decoupling Layout

100nF cap placed directly against the IC, oriented with pads facing the IC pins. Via-in-pad on both cap pads connects directly to power and ground planes. Total loop inductance measured at 0.15 nH. Four such caps distributed around the IC with equal spacing provide broadband decoupling from 10 MHz to 1 GHz.

Bad: Poor Decoupling Layout

100nF caps placed 5mm from the IC "for assembly access." Long traces connect caps to IC pins. Single shared via serves 4 capacitors. Thermal relief on ground connection. Measured loop inductance: 3 nH. Caps ineffective above 50 MHz - the band where the IC actually needs decoupling.

Checkpoint: Sense Trace Routing (Kelvin Connection)

Review Criteria

Voltage sense (feedback) traces for regulators are routed as Kelvin connections directly from the load point, not from the regulator output. Sense traces are thin (no current flowing), separated from power traces, and protected from noise coupling.

Kelvin Connection Principles

A Kelvin (4-wire) connection separates the current-carrying path from the voltage-sensing path. This eliminates the IR drop in the power traces from affecting the regulation accuracy.

WRONG: Sense from regulator output

  [Regulator OUT] ---50mm heavy trace--- [Load IC]
       |
       +-- Feedback to regulator

  Problem: Regulator "sees" its own output voltage, not the load voltage.
  If IR drop = 50mV, load gets 50mV less than intended.

CORRECT: Kelvin sense from load point

  [Regulator OUT] ---50mm heavy trace--- [Load IC]
                                              |
                                              +-- thin sense trace back to regulator FB pin

  Regulator adjusts output to compensate for IR drop.
  Load voltage is precisely at target.

Sense Trace Routing Rules

Route sense trace directly from the IC power pin (or closest decoupling cap connection point)
Keep sense trace thin (4-5 mil) - it carries no current, only senses voltage
Do not share the sense trace copper with any current-carrying path
Route sense trace away from switching nodes and high-di/dt traces
If sense trace is long, add a small filter cap (10-100pF) at the regulator feedback pin
For remote sensing across a connector, route sense wires as a dedicated pair

Common Pitfall: Feedback Tapped from Wrong Location

The voltage divider for a buck regulator's feedback is connected to the output inductor node (regulator side) instead of after the output capacitors (load side). This means the regulation point is before the output filter, and any voltage drop across the output caps and PCB traces is uncompensated. Always connect the top of the feedback divider at the point of load, not at the regulator output pin.

Checkpoint: Star-Point Connection for Current Measurement

Review Criteria

Current sense resistors use 4-terminal (Kelvin) connection. Sense traces connect at the resistor pad edge closest to the measurement point, not through shared copper. Star-point grounding used where multiple return currents must not share paths.

Current Sense Resistor Layout

CORRECT: Kelvin connection to sense resistor

         FORCE+ (high current)           FORCE- (high current)
  ==========[Rsense Pad 1]====[Rsense Pad 2]==========
                  |                        |
              SENSE+                   SENSE-
              (to amplifier)           (to amplifier)

  Sense traces tap from the INNER edge of each pad.
  No current flows through the sense traces.
  Amplifier measures only the voltage across the resistor element.

WRONG: Shared copper sense

  =====[Rsense]====
     |           |
  SENSE+      SENSE-

  Sense point includes trace resistance before/after resistor.
  Measurement error proportional to shared copper resistance.

Star-Point Ground Applications

Multiple ADC channels: Each channel's ground reference returns independently to the ADC ground pin
Mixed-signal circuits: Analog ground and digital ground meet at a single point (typically under the IC)
Current measurement: Sense amplifier ground connects directly to the sense resistor ground pad
Multi-output power supply: Each output's return connects to a common star point to prevent cross-regulation errors

Checkpoint: Fuse/Switch Placement for Service Access

Review Criteria

Fuses, circuit breakers, and power switches are placed in accessible locations for field service. Power sequencing switches are positioned to minimize trace length to their loads. Fuse holders allow replacement without board removal.

Power Protection Component Placement Rules

Component	Placement Requirement	Routing Consideration
Board fuse (SMD)	Near power entry connector	Before any other components on that rail
Fuse holder (through-hole)	Board edge, accessible	Short, wide traces to handle fault current
Power switch (MOSFET)	Between source and load	Minimize gate drive trace length, kelvin source sense
eFuse IC	Near input connector	Input cap before eFuse, output cap after
TVS/Zener protection	At connector pins	Shortest path from protected pin to ground
Polarity protection	Immediately after connector	Full current rating traces/planes

Thermal Considerations for Power Switches

Power MOSFETs and eFuse ICs dissipate significant power during operation and especially during fault conditions:

Provide adequate thermal vias under thermal pads (see Tutorial 5.4)
Keep sensitive components away from power switch thermal zone
Ensure copper pour on the power path layer provides heat spreading
For hot-swap controllers: design for full inrush current thermal stress

Industry Standards References

IPC-2221B Section 6: Current carrying capacity and conductor sizing
IPC-2152: Standard for Determining Current-Carrying Capacity in Printed Board Design (replaced old IPC-2221 charts)
IPC-9592B: Requirements for Power Conversion Devices for the Computer and Telecommunications Industries
JEDEC JESD158: Power and Ground Plane Structure for High Speed Clock Signal Design
IEC 60127: Miniature fuses - PCB fuse requirements and derating

Power Layout Review Summary

Quick Verification Checklist

Run IR-drop simulation for all power rails carrying more than 500mA
Verify plane shape coverage extends to all loads with no islands
Check plane-to-plane clearance between different voltage domains
Inspect all plane bottlenecks - ensure minimum cross-section meets current needs
Verify decoupling cap via placement follows IC-side-first rule
Confirm no thermal relief on power/ground decoupling connections
Check sense trace routing is Kelvin (from load point, not regulator output)
Verify star-point connections where multiple returns converge
Confirm fuses are first in the power chain after the connector
Run thermal simulation for power components under full load

Common Fabricator Power Layout Notes

Parameter	Value	Notes
Minimum power trace width for 1A	10 mil (external) / 20 mil (internal)	For 10C rise on FR-4
Plane copper pullback from edge	20 mil (0.5mm)	Prevents copper exposure at routed edge
Minimum plane clearance	8 mil between power domains	Fabricator-dependent; some require 10-12 mil
Thermal relief spoke width	8-12 mil typical	Only for thermal management; not for decoupling
Via connection to plane	Direct connect for power	No thermal relief for current-carrying connections

Power Plane Design Techniques

Thermal Relief vs Direct Connect

THERMAL RELIEF (for hand-soldering / rework):
  Used when: Through-hole components that need hand soldering
  Pattern: 4 spokes connecting pad to plane
  Spoke width: 8-12 mil minimum
  Gap width: 10-15 mil between spokes

      ====+    +====        + = copper plane
          |    |            | = spoke
     --[  PAD  ]--          - = gap
          |    |
      ====+    +====

DIRECT CONNECT (for power delivery / decoupling):
  Used when: Maximum current capacity needed, via connections for decoupling
  Pattern: Full solid connection between pad and plane
  No gaps, no spokes - lowest possible resistance

      ================
      ====[ PAD ]====       Full copper flood around pad
      ================

Rule: Power vias and decoupling cap vias ALWAYS get direct connect.
      Only use thermal relief for through-hole pins that need hand rework.

Split Power Plane Design

When multiple voltage domains share a single power plane layer:

Plan the split geometry: Sketch voltage regions based on component placement before routing
Maintain minimum clearance: 8-20 mil between domains depending on voltage difference
Avoid signal crossings: No high-speed signal should cross between two power domain boundaries
Connect at a single point: Each domain connects to its regulator output via a clean, wide path
Fill remaining area with ground: Any unused area on a split power layer should be ground fill (stitched to other ground layers)

Power Polygon Routing Example

Typical Power Layer (Layer 4) with 3 voltage domains:

+------------------------------------------------------------------+
|                                                                    |
|   +==================+     +=====================+                |
|   |                  |     |                     |                |
|   |   VCC_3V3       |     |    VCC_1V8          |                |
|   |   (Regulator    |     |    (DDR Memory      |                |
|   |    output here) | gap |     supply)          |                |
|   |                  |     |                     |                |
|   +==================+     +=====================+                |
|                                                                    |
|              gap (8-20 mil)                                        |
|                                                                    |
|   +==========================================================+    |
|   |                                                          |    |
|   |              VCC_1V0 (Core supply)                       |    |
|   |              Wide polygon under processor                 |    |
|   |                                                          |    |
|   +==========================================================+    |
|                                                                    |
|   Remaining area: GND fill (stitched to other GND layers)         |
|                                                                    |
+------------------------------------------------------------------+

Tool-Specific Power Layout Instructions

Altium Designer - Power Plane Design

Create polygon pour: Place > Polygon Pour on the power layer
Assign net: set polygon net to the voltage domain (e.g., VCC_3V3)
Set connect style: Properties > Connect Style = Direct Connect for power connections
Pour clearance: set per-polygon or use design rules
Fill remaining area: create a second polygon assigned to GND with lower priority
Use PDN Analyzer: Tools > PDN Analyzer to verify voltage drop

KiCad - Zone-Based Power

Draw zone: Place > Zone on the power layer
Assign net in zone properties dialog
Set zone priority (higher number fills first in overlapping areas)
Pad connections: set to "Solid" for power vias, "Thermal Relief" only for rework pads
Fill all zones: Edit > Fill All Zones (B shortcut)
Check for islands: Inspect > Board Statistics or DRC

Cadence Allegro - Power Shapes

Create dynamic shape: Shape > Dynamic Copper on power layer
Assign net via shape properties
Set void controls: Shape > Global Dynamic Shape Parameters
Thermal relief: configure per-net in Constraint Manager
Check for isolated islands: Shape > Check > Isolated shapes
Run IR Drop analysis: Analyze > IR Drop (Sigrity PowerDC integration)

Common Pitfall: Isolated Copper Islands in Power Plane

When a power plane is fragmented by dense via fields (e.g., under a BGA), small isolated copper islands can form that are not connected to the source. These islands are electrically floating, which means components connected to them have no power supply. The DRC should catch these as "isolated copper" or "split plane" violations. Always run DRC after regenerating plane shapes, and visually inspect plane layers for islands near dense via areas.

Tutorial 5.5: Power Distribution Layout

Introduction to Power Distribution Layout

PDN Design Hierarchy

Checkpoint: Power Plane Shapes Adequate

Review Criteria

Power Plane Design Rules

Voltage Drop Calculation for Power Traces

Current Density Visualization

Altium Designer - PDN Analyzer

Cadence Allegro - PowerDC/Sigrity

KiCad - External Tools

Good: Well-Designed Power Shape

Bad: Bottlenecked Power

Checkpoint: No Bottlenecks in Power Paths

Review Criteria

Common Bottleneck Locations

How to Identify Bottlenecks

Common Pitfall: Signal Via Field Fragmenting Power Plane

Checkpoint: Decoupling Cap Via Placement Optimal

Review Criteria

Optimal Via Placement Patterns

Critical Rules for Decoupling Via Connections

Good: Optimized Decoupling Layout

Bad: Poor Decoupling Layout

Checkpoint: Sense Trace Routing (Kelvin Connection)

Review Criteria

Kelvin Connection Principles

Sense Trace Routing Rules

Common Pitfall: Feedback Tapped from Wrong Location

Checkpoint: Star-Point Connection for Current Measurement

Review Criteria

Current Sense Resistor Layout

Star-Point Ground Applications

Checkpoint: Fuse/Switch Placement for Service Access

Review Criteria

Power Protection Component Placement Rules

Thermal Considerations for Power Switches

Industry Standards References

Power Layout Review Summary

Quick Verification Checklist

Common Fabricator Power Layout Notes

Power Plane Design Techniques

Thermal Relief vs Direct Connect

Split Power Plane Design

Power Polygon Routing Example

Tool-Specific Power Layout Instructions

Altium Designer - Power Plane Design

KiCad - Zone-Based Power

Cadence Allegro - Power Shapes

Common Pitfall: Isolated Copper Islands in Power Plane