Tutorial 5.3: Routing Rules & Constraints

Introduction to Routing Rules

Routing rules and constraints are the DNA of a well-designed PCB. They translate electrical requirements (impedance, timing, voltage isolation) into physical parameters (trace width, spacing, length) that the designer and DRC engine enforce during layout. A design without properly configured constraints is relying solely on the designer's memory and discipline - both of which fail under schedule pressure.

Rule Hierarchy

1. Default rules: Baseline minimum values for the entire design (manufacturing minimum)
2. Net class rules: Override defaults for specific groups of nets (e.g., "Power" class, "High-Speed" class)
3. Net-specific rules: Override net class for individual critical nets
4. Region-specific rules: Override all above within a defined board region (e.g., BGA breakout zone)

Checkpoint: Minimum Trace Width Per Net Class

Net Class Width Definitions

Manufacturer Minimum Capabilities

Step-by-Step Width Rule Setup

1. Define net classes based on function (Power_3V3, Power_1V8, USB_HS, DDR_Data, General_Signal)
2. Assign all nets to appropriate classes (no orphan nets in "Default" unless truly default)
3. Calculate required widths for power nets using IPC-2152 or Saturn PCB Toolkit
4. Calculate impedance-controlled widths from field solver for signal nets
5. Set minimum width rule for each class
6. Set preferred width (used by auto-router and interactive width selection)
7. Run DRC to verify no violations exist

Checkpoint: Clearance Rules Set Per Voltage

IPC-2221B Clearance Requirements (Sea Level, Uncoated)

Safety Standard Creepage/Clearance (IEC 62368-1)

For mains-connected equipment, additional safety clearances apply:

How to Configure Voltage-Based Clearance

1. Identify all voltage domains in the design and their maximum voltages
2. Calculate clearance requirements between each voltage domain pair
3. Configure clearance rules that apply to specific net-to-net combinations
4. Pay special attention to:
   • Mains AC to low-voltage DC (reinforced insulation required)
   • High-voltage power supply output to logic signals
   • Battery terminals to chassis/ground
   • ESD protection devices (high transient voltages)
5. Verify clearance is maintained on ALL layers (including internal layers at vias)

Checkpoint: Differential Pair Routing with Tight Coupling

Differential Pair Parameters by Interface

Differential Pair Routing Best Practices

1. Maintain constant spacing: The space between P and N traces must not vary by more than 10% along the route
2. Symmetric bends: When the pair turns, both traces must bend identically. Use coupled-mode routing, not individual trace routing
3. No reference plane gaps: Never route a diff pair over a plane split or gap. The return path disruption destroys impedance and balance
4. Via transitions in pairs: Both P and N vias must be placed symmetrically, with identical GND return vias adjacent
5. Length matching: Match within each pair first (intra-pair), then match between pairs in the same interface (inter-pair)
6. Breakout from IC: Begin tight coupling as soon as both traces clear the IC pad field

Checkpoint: Length Matching Groups Defined

Length Matching Requirements by Interface

Serpentine Tuning Rules

Serpentine Quality Guidelines:
================================
Amplitude (A):  1x to 3x trace width (typically 3W max)
Spacing (S):    >= 3x trace width (to avoid self-coupling)
Gap (G):        >= 4x trace width (between adjacent serpentines)

Example for 5-mil trace:
  Amplitude: 5-15 mil
  Spacing:   >= 15 mil
  Gap:       >= 20 mil

GOOD serpentine:       BAD serpentine:
  _     _     _         __    __    __
 | |   | |   | |       |  |  |  |  |  |
 | |   | |   | |       |  |  |  |  |  |
 |_|   |_|   |_|       |__|  |__|  |__|

 S=3W, A=2W            S=1W, A=5W
 Low self-coupling     High self-coupling
 Minimal impedance     Significant Z change
 impact                and crosstalk
            

Checkpoint: No Acute Angles (45-degree or Arc Preferred)

Trace Angle Guidelines

The 90-Degree Corner Myth

While frequently cited as a major signal integrity issue, 90-degree corners have negligible electrical impact below 10 GHz. The actual impedance change at a 90-degree corner is approximately 15% over a distance of the trace width - typically less than 0.1 ps of timing impact. However, 90-degree corners are avoided because:

• Manufacturing: Sharp outer corners can cause over-etching
• DFM: Inner corners create potential acid traps
• Professional practice: 45-degree routing looks more professional and is easier to modify
• High frequency (>10 GHz): Becomes electrically significant for mmWave designs

Checkpoint: Trace Entry to Pads Centered

Pad Entry Requirements

• Trace must connect to pad with minimum annular ring maintained on all sides
• For SMD pads, trace enters from the short side (width direction) when possible
• Trace width at pad entry should not exceed 80% of pad width (prevents tombstoning)
• Symmetric trace entry for opposing pads on passives (both traces same width, same entry angle)
• Teardrops recommended at all via-to-trace connections and at SMD pad entries in high-reliability designs

Teardrop Benefits

1. Eliminates potential acid trap at trace-pad junction
2. Provides manufacturing margin for drill-to-copper registration
3. Reduces stress concentration that can cause trace fracture during thermal cycling
4. IPC Class 3 designs often require teardrops at all connections

Checkpoint: Neck-Down Rules at BGA Escape

BGA Fan-Out Strategies

BGA Escape Routing Techniques

1.0mm Pitch BGA - Dog-Bone Fan-Out:

    O   O   O   O   O      O = BGA Pad
    |   |   |   |   |      | = Short trace to via
    v   v   v   v   v      v = Via (dog-bone)

  Row 1: All pads escape directly down to via on same layer or adjacent layer
  Row 2: Route between Row 1 pads (1 trace channel)
  Row 3: Route through via field (requires inner signal layers)
  Row 4+: Must use inner layers (blind/buried vias or through-hole vias)

Via-in-Pad (0.8mm and below):
  No dog-bone needed - via is IN the pad
  Requires via fill + planarization (adds cost)
  Enables escape from any row on inner layers directly
            

Neck-Down Rule Configuration

1. Define a "BGA Breakout" region/room around each BGA component
2. Create width/space rules for this region that allow reduced values:
   • Width: manufacturing minimum (3.5-4 mil typically)
   • Space: manufacturing minimum (3.5-4 mil typically)
3. These region rules override the default net class rules ONLY within the BGA area
4. Traces return to full width (impedance-controlled) once they exit the breakout zone
5. Document the neck-down zone clearly for DRC review (short neck-down lengths minimize impedance impact)

Routing Rules Configuration Summary

Complete Rule Set Template

A well-configured design should have the following constraint categories defined:

DRC Rule Configuration Checklist

1. Minimum trace width: Set to fabricator minimum (never below 3.5mil for standard fabs)
2. Minimum clearance: Set to fabricator minimum (never below 3.5mil)
3. Power net widths: Calculated from IPC-2152 for required current/temperature rise
4. Impedance-controlled widths: Calculated from field solver based on stackup
5. Differential pair rules: Width, spacing, max skew per interface specification
6. Length matching: Groups defined per interface, tolerances per specification
7. Voltage-based clearance: IPC-2221B or IEC 62368-1 per voltage difference
8. BGA breakout region: Reduced rules for escape routing with fabricator approval
9. Annular ring: Minimum per IPC-6012 class (4mil for Class 2, same for Class 3)
10. Acid trap angle: No angles less than 90 degrees at trace junctions

BGA Fan-Out Strategy Comparison

Strategy 1: Dog-Bone (Standard Through-Via)
=============================================
Pitch: 1.0mm | Pad: 0.5mm | Via: 0.3mm drill / 0.6mm pad

  Outer 2 rows: Escape on surface layer via dog-bone
  Inner rows: Via down, escape on inner signal layers
  Pros: Simple, standard process, low cost
  Cons: Uses signal layer area below BGA

Strategy 2: Via-in-Pad (HDI)
============================
Pitch: 0.8mm or less | Pad: 0.35-0.4mm | Via: 0.1mm laser drill

  All rows: Via directly in BGA pad (microvia to next layer)
  Escape on layer 2 (immediately below)
  Pros: Enables fine-pitch escape, no surface routing needed
  Cons: Higher cost (laser drill + fill + plate)

Strategy 3: Dog-Bone with Channel Routing
==========================================
Pitch: 1.0mm | 1-2 traces between pads

  Row 1: Direct escape (no via, route to perimeter on top layer)
  Row 2: Dog-bone via, escape between Row 1 pads
  Row 3-4: Route down to inner layer, channel between vias
  Rows 5+: Must use dedicated inner signal layers

  Channel Capacity:
    1.0mm pitch, 0.5mm pad: gap = 0.5mm
    Trace+Space: 4+4 mil = 8mil = 0.2mm per channel
    Channels between pads: 2 (with 0.1mm margin)
            

Routing Rules Verification Procedure

1. Export the complete design rule set as a document/report
2. Verify each rule against its justification:
   • Width rules: vs IPC-2152 calculation or impedance calculation
   • Clearance rules: vs IPC-2221B table or safety standard
   • Length matching: vs interface specification datasheet
3. Confirm no rules conflict (e.g., net class rule wider than region rule allows)
4. Run DRC with ALL rules enabled to verify compliance
5. Document any waivers or exceptions with engineering justification