Checkpoint 1: Minimum Trace/Space Within Fab Class Critical
Every trace width and clearance on the PCB must meet the fabricator's manufacturing capability for the chosen technology class. Violating these minimums results in opens, shorts, and reduced yield.
IPC-6012 Classification vs. Fabrication Capability
| Parameter | Class 2 (Standard) | Class 3 (High Reliability) | HDI (Advanced) | Ultra-HDI |
|---|
| Minimum trace width | 100µm (4mil) | 75µm (3mil) | 50µm (2mil) | 25µm (1mil) |
| Minimum space | 100µm (4mil) | 75µm (3mil) | 50µm (2mil) | 25µm (1mil) |
| Minimum via drill | 200µm (8mil) | 150µm (6mil) | 100µm (4mil) | 50µm (2mil) |
| Annular ring (external) | 50µm (2mil) | 50µm (2mil) | 38µm (1.5mil) | 25µm (1mil) |
| Annular ring (internal) | 25µm (1mil) | 25µm (1mil) | 25µm (1mil) | 12µm (0.5mil) |
| Solder mask registration | 75µm (3mil) | 50µm (2mil) | 38µm (1.5mil) | 25µm (1mil) |
| Board thickness tolerance | ±10% | ±10% | ±8% | ±5% |
| Typical cost multiplier | 1× | 1.3-1.5× | 2-4× | 5-10× |
Step-by-Step DFM Check
- Determine your PCB technology class based on the finest-pitch component. Example: 0.4mm pitch BGA requires 3/3mil trace/space minimum.
- Obtain your fabricator's actual capability list (not just IPC minimums). Each fab has specific limits based on their equipment.
- Set design rules in your EDA tool to match or exceed the fabricator's minimums (with 10-20% margin preferred).
- Run DRC (Design Rule Check) and resolve ALL violations. No manual overrides on trace/space rules.
- Verify critical areas manually: BGA fan-out regions, fine-pitch IC breakouts, high-voltage clearances.
- Submit Gerber files to fabricator for DFM review before ordering. Most fabs offer free DFM checks.
BGA Fan-Out Calculation:
For a BGA with pitch P, pad diameter D, and n routing channels between pads:
Available space between pads: S = P - D
Required per channel: trace_width + 2 × clearance
Number of channels possible: n = floor(S / (trace + 2×clear))
Example: 0.8mm pitch BGA, pad diameter 0.4mm
Available: S = 0.8 - 0.4 = 0.4mm = 400µm
With 4mil/4mil (100/100µm): channel = 100 + 200 = 300µm → 1 trace possible
With 3mil/3mil (75/75µm): channel = 75 + 150 = 225µm → 1 trace (with 175µm remaining)
Example: 0.5mm pitch BGA, pad diameter 0.275mm
Available: S = 0.5 - 0.275 = 0.225mm = 225µm
With 3mil/3mil: channel = 225µm → EXACTLY 1 trace (no margin)
With 2.5mil/2.5mil: channel = 188µm → 1 trace with 37µm margin ✓
0.5mm BGA requires HDI capability (3mil minimum, 2.5mil preferred)
Design uses 4mil/4mil trace/space as the minimum, targeting fabricators with 3.5mil capability (0.5mil manufacturing margin). BGA fan-out area is annotated in design notes as "HDI zone -- 3mil/3mil minimum here, verify with fab." Design rules have a separate constraint class for the BGA area. Fabricator DFM review confirms: "No violations found, design is within our standard capability."
Design has 2mil traces in BGA fan-out to fit routing. The chosen fabricator's minimum is 3mil. Fabricator quotes as "advanced HDI" with 3× price increase and 4-week additional lead time. Alternatively, some 2mil traces are fabricated undersize, causing intermittent opens after thermal cycling.
- Inner layer registration: Inner layer trace/space must account for ±50µm (2mil) layer-to-layer registration. A 4mil trace can shift by 2mil relative to the layer above/below.
- Copper weight impact: 2oz copper requires wider trace/space (typically 5mil minimum vs. 4mil for 1oz) due to etching undercut being proportional to copper thickness.
- Differential pairs: Differential pairs need consistent space (coupling gap) which may be tighter than general clearance rules. Verify separately.
- Etch compensation: Outer layers etch differently than inner layers. A "4mil" design rule may need 4.5mil on outer and 3.5mil on inner to achieve 4mil finished.
Checkpoint 2: Annular Ring Meets IPC-6012 Critical
The annular ring is the copper remaining around a drilled via or pad hole. Insufficient annular ring results in breakout (drill missing the pad), causing opens or unreliable connections on inner layers.
Annular Ring Calculation:
AR = (Pad_diameter - Drill_diameter) / 2
Minimum Requirements (IPC-6012):
External layers (Class 2): 50µm (2mil) minimum after etch
External layers (Class 3): 50µm (2mil) minimum after etch
Internal layers (Class 2): 25µm (1mil) minimum
Internal layers (Class 3): 50µm (2mil) minimum
Practical Design Rule (include drill tolerance):
AR_design = AR_min + Drill_tolerance/2 + Registration_tolerance
Example: 0.3mm (12mil) drill, 0.6mm (24mil) pad
AR_nominal = (0.6 - 0.3) / 2 = 0.15mm = 150µm = 6mil
Drill tolerance: ±50µm (±2mil)
Registration: ±50µm (±2mil)
AR_worst_case = 150 - 25 - 50 = 75µm (3mil) -- Meets Class 2/3 ✓
Example: 0.2mm (8mil) drill, 0.35mm (14mil) pad
AR_nominal = (0.35 - 0.2) / 2 = 0.075mm = 75µm = 3mil
AR_worst_case = 75 - 25 - 50 = 0µm -- TANGENT! May break out!
Need 0.4mm (16mil) pad minimum for 0.2mm drill
Annular Ring by Via Type
| Via Type | Typical Drill | Min Pad (Class 2) | Min Pad (Class 3) | Recommended Pad |
|---|
| Standard through-via | 0.3mm | 0.5mm | 0.55mm | 0.6mm |
| Small through-via | 0.2mm | 0.35mm | 0.4mm | 0.45mm |
| Microvia (laser) | 0.1mm | 0.2mm | 0.25mm | 0.25mm |
| Through-hole comp | 0.8mm | 1.1mm | 1.2mm | 1.3mm |
| Mounting hole | 3.2mm | 3.7mm | 3.8mm | 4.0mm |
All vias designed with minimum 0.15mm (6mil) annular ring on outer layers and 0.1mm (4mil) on inner layers. Via pads: 0.3mm drill → 0.6mm pad, 0.2mm drill → 0.45mm pad. Design rule check confirms zero annular ring violations. Fabricator confirms adequate margin for their drill wander specification.
0.25mm vias with 0.4mm pads (75µm nominal AR) placed in dense BGA area. Due to drill wander and registration, 15% of inner-layer connections have breakout. Board functions intermittently -- some vias make contact through solder filled in the barrel but have high resistance. Failures appear during thermal cycling as the solder connection degrades.
Checkpoint 3: Aspect Ratio Within Capability Major
The aspect ratio (board thickness divided by drill diameter) determines plating reliability. High aspect ratios make it difficult to achieve uniform copper plating through the via barrel, leading to thin spots and reliability issues.
Aspect Ratio = Board_Thickness / Drill_Diameter
Standard fabricator limits:
Standard fab: AR ≤ 8:1 (preferred ≤ 6:1)
Advanced fab: AR ≤ 10:1
HDI fab: AR ≤ 12:1 (for mechanical drill)
Laser microvia: AR ≤ 1:1 (depth ≤ diameter)
Example check:
Board thickness: 1.6mm, smallest drill: 0.2mm
AR = 1.6 / 0.2 = 8:1 -- At standard fab limit
Board thickness: 2.4mm (8-layer), smallest drill: 0.25mm
AR = 2.4 / 0.25 = 9.6:1 -- Requires advanced fab!
Solutions for high AR:
1. Increase minimum drill size (0.3mm instead of 0.2mm)
2. Reduce board thickness (backdrilling, thinner prepregs)
3. Use blind/buried vias (reduced depth)
4. Use sequential lamination with microvias
Plating Reliability vs. Aspect Ratio
| Aspect Ratio | Min Plating (barrel center) | Reliability Risk | Cost Impact |
|---|
| ≤ 6:1 | 25µm (1mil) | Low | Standard pricing |
| 7:1 - 8:1 | 20µm (0.8mil) | Moderate | Standard pricing |
| 9:1 - 10:1 | 15µm (0.6mil) | High | 10-20% premium |
| 11:1 - 12:1 | 12µm (0.5mil) | Very High | 30-50% premium |
| > 12:1 | May be unplatable | Extreme | Special process required |
- Thick boards with small vias: An 8-layer board at 2.0mm thickness with 0.2mm vias = 10:1 AR. Either increase drill or use blind vias for signal routing.
- Plating voids: High AR vias may have plating voids in the barrel center. These create intermittent connections that pass initial test but fail under thermal stress.
- IPC Class 3 impact: Class 3 requires minimum 25µm plating throughout the barrel, which may not be achievable at AR > 8:1 with standard chemistry.
- Impedance impact: Thin plating increases via resistance and inductance. For high-speed signals, this affects signal integrity at GHz frequencies.
Checkpoint 4: Copper Balance Across Layers Major
Uneven copper distribution across layers causes board warpage during lamination and reflow. The copper on each layer should be balanced to within 15-20% for reliable flatness.
Copper Balance Assessment:
Calculate copper percentage for each layer:
Cu% = (Total copper area on layer) / (Board area) × 100%
Balance requirement:
Symmetric pairs (L1↔L_n, L2↔L_{n-1}, etc.) should match within ±15%
Overall average should be 40-70% per layer
Example: 4-layer board (100mm × 80mm = 8000mm²)
L1 (signal + components): Cu = 35% (2800mm²)
L2 (ground plane): Cu = 85% (6800mm²)
L3 (power plane): Cu = 75% (6000mm²)
L4 (signal + components): Cu = 40% (3200mm²)
Balance check:
L1 vs L4: 35% vs 40% → Δ=5% ✓ (good symmetry)
L2 vs L3: 85% vs 75% → Δ=10% ✓ (acceptable)
Problematic example:
L1: 20% (sparse signal routing)
L2: 90% (full ground plane)
L3: 90% (full power plane)
L4: 80% (mostly ground pour)
L1 vs L4: 20% vs 80% → Δ=60% -- SEVERE IMBALANCE!
Board will bow toward L1 (less copper, more shrinkage)
Solutions for Copper Imbalance
- Add copper thieving (balancing patterns): Add non-functional copper dots, hatches, or fills to sparse layers. Typically 1-2mm dots on 3mm grid.
- Use hatched fills instead of solid fills: If one layer must be sparse, make the opposing layer hatched (50-70%) instead of solid (90%).
- Balance signal layers: If L1 is sparse, add ground pour fill around signal traces to increase copper percentage.
- Thieving in panel borders: Add copper balance patterns in non-functional areas (outside board outline, in routing tabs).
Copper fill analysis performed before fab release: L1=52%, L2=82%, L3=78%, L4=48%. Symmetric pairs: L1/L4 differ by 4%, L2/L3 differ by 4%. Copper thieving added to L1 and L4 signal layers (2mm dots on 3mm grid in open areas) to increase from 35%/40% to 52%/48%. Fabricator confirms board meets IPC-6012 bow/twist specification (<0.75%).
No copper balance check performed. One-sided design has components only on top: L1=25% (signals), L2=90% (GND), L3=90% (PWR), L4=90% (GND). Bottom side is almost entirely copper. Board warps concave toward component side. Surface mount assembly fails because warpage exceeds 0.75% of diagonal, and fine-pitch components have open solder joints.
Checkpoint 5: Acid Traps Eliminated Major
Acid traps are acute angles (less than 90°) in copper features where etching chemicals can become trapped, causing over-etching and trace thinning or opens. They must be identified and eliminated.
What Causes Acid Traps
Acid trap geometry:
An acid trap forms when two copper features meet at an acute angle
(less than 90°), creating a pocket where etchant pools.
Common locations:
1. Trace connecting to pad at acute angle (trace entering pad tangentially)
2. Two traces meeting at < 90° angle
3. Trace meeting a copper pour at a sharp point
4. Mitered corners that create pointed features
Rule: No internal angle less than 90° in any copper feature.
Preferred: All angles ≥ 135° (use curved traces or 45° routing)
Detection and Prevention
- Run your EDA tool's DFM check for acid traps (most modern tools have this built in).
- Visually inspect areas where traces connect to pads at non-orthogonal angles.
- Check pour/fill connections to traces -- pour can create acute-angle junctions.
- Eliminate by: changing trace entry angle, adding teardrops to pad connections, or moving via/pad location.
- Use 45° routing style (Manhattan + 45°) instead of arbitrary angles to reduce acid trap risk.
- Enable teardrop insertion in your EDA tool for all pad-trace and via-trace connections.
All trace-to-pad connections have teardrops enabled (minimum teardrop length 0.2mm). Routing style set to 45° only (no arbitrary angles). DFM acid trap check runs clean. Pour connections use thermal relief spokes at 45°/90° angles (no acute angles possible).
Manual routing with arbitrary angles. A signal trace enters a via pad at 15° to the horizontal, creating a sharp pointed copper feature. During etching, this point is over-etched, creating a narrow neck that increases resistance and eventually fails under thermal cycling.
Checkpoint 6: Solder Mask Slivers Removed Major
Solder mask slivers are very narrow strips of solder mask between copper features. If the sliver is too narrow (typically < 75µm / 3mil), it may detach during processing, causing solder bridges or cosmetic defects.
Solder Mask Sliver Minimum:
Standard: ≥ 75µm (3mil) solder mask web between openings
Preferred: ≥ 100µm (4mil) for reliable registration
Maximum registration tolerance: ±50µm (±2mil) for standard LDI process
Sliver calculation:
SM_web = Copper_clearance - 2 × SM_expansion
Example: Two SMD pads 0.2mm apart, SM expansion = 0.05mm per side:
SM_web = 0.2 - 2×0.05 = 0.1mm = 100µm ✓
Example: Two pads 0.15mm apart, SM expansion = 0.05mm:
SM_web = 0.15 - 2×0.05 = 0.05mm = 50µm -- TOO NARROW!
Solution: Remove solder mask between pads (one opening for both)
When to Remove Solder Mask Between Pads
| Pad Spacing | SM Web (with ±50µm tolerance) | Action |
|---|
| ≥ 200µm (8mil) | ≥ 100µm ✓ | Keep solder mask dam between pads |
| 150-200µm (6-8mil) | 50-100µm (marginal) | Reduce SM expansion or combine openings |
| < 150µm (6mil) | < 50µm (too narrow) | Combine into one SM opening (remove dam) |
| 0.4mm pitch QFP | ~100µm (marginal) | Verify with fab, may need 0 expansion |
| 0.3mm pitch BGA | ~50µm (insufficient) | Non-solder mask defined (NSMD) pads |
For fine-pitch IC (0.5mm pitch QFP, pad width 0.3mm, gap 0.2mm): Solder mask expansion set to 0.04mm (1.6mil). SM web = 0.2 - 2×0.04 = 0.12mm = 4.7mil. Fabricator minimum SM web = 3mil. Margin = 1.7mil over minimum. Acceptable for production.
Standard 0.05mm SM expansion applied globally, including 0.4mm pitch QFP (pad gap = 0.15mm). SM web = 0.15 - 0.1 = 0.05mm = 2mil. Below fabricator minimum. Solder mask slivers peel off during reflow, causing solder bridges between adjacent IC pins. Yield drops to 60%.
Checkpoint 7: Panel Step-and-Repeat Considered Minor
For production volumes, PCBs are fabricated in panels containing multiple copies of the board. The panelization design affects cost, assembly efficiency, and board quality.
Panelization Design Guidelines
Standard panel sizes:
18" × 24" (457 × 610mm) -- Most common for production
16" × 18" (406 × 457mm) -- Common for smaller fabs
12" × 18" (305 × 457mm) -- Prototype panels
Utilization calculation:
N_boards = floor((Panel_X - 2×rail) / (Board_X + gap)) ×
floor((Panel_Y - 2×rail) / (Board_Y + gap))
Example: 50mm × 80mm board on 457×610mm panel
Rail = 5mm per side, gap = 2mm (V-score) or 0mm (tab route)
N_X = floor((457 - 10) / (50 + 2)) = floor(8.6) = 8
N_Y = floor((610 - 10) / (80 + 2)) = floor(7.3) = 7
N_total = 8 × 7 = 56 boards per panel
Utilization = (56 × 50 × 80) / (457 × 610) = 80.5%
Target: >70% utilization for good cost efficiency
Depanelization Methods
| Method | Edge Quality | Stress on Board | Minimum Clearance | Best For |
|---|
| V-score (V-groove) | Good (smooth) | Low (flex) | 0.5mm from features | Rectangular boards |
| Tab routing (breakaway) | Fair (mouse bites) | Moderate | 3-5 tabs, 2-3mm from edge | Irregular shapes |
| Router (full separation) | Excellent | None (pre-separated) | 1.6mm router bit kerf | High-quality edges |
| Laser depanel | Excellent | None | 0.1mm kerf | Flex circuits, HDI |
| Perforated tabs (jump score) | Good | Low-moderate | 3mm from features | Thick boards |
- Determine board outline and any keep-out areas near edges for depanelization clearance.
- Choose depanelization method based on board shape, edge quality requirements, and component proximity to edges.
- Design panel with tooling rails (5mm minimum width) containing fiducial marks, tooling holes, and test coupons.
- Add breakaway tabs or V-score lines. For tabs: 3-5 tabs per edge, 3-5mm wide, with perforations (mouse bites).
- Ensure no components within 3mm of V-score line or 5mm of breakaway tab (to avoid stress damage).
- Include test coupons for impedance verification, microsection analysis, and solder paste inspection.
Panel design submitted with assembly file: 4×3 array of boards (12-up), V-scored on all straight edges. 5mm tooling rails with 3 fiducials (global) and 2 local fiducials per board. Tooling holes at panel corners (3.2mm, plated). No components within 1mm of V-score. Break tabs with 5× 0.5mm drill holes (mouse bites) on two irregular edge sections.
Single board ordered without panelization consideration. Assembly house manually panels the board with insufficient clearance -- V-score passes within 0.3mm of an edge-mounted connector. During depanelization, the stress cracks the connector solder joint. 8% assembly fallout rate due to this issue.
